Open Superblock Read Trim Selection for Partial Writes

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Solution Overview

Problem

Existing memory systems face challenges in efficiently handling partially written superblocks, leading to increased uncorrectable bit error rates and complexity in system controllers due to cell-to-cell interference and inadequate read trim set management.

Innovation Solution

A memory device is configured to maintain internal status of open superblocks, including a page indicator for the last written page, allowing it to determine the appropriate read trim set for partially written superblocks based on page map information and last written page status, thereby reducing errors and controller complexity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If traditional read operations are used on partially written superblocks, then read operations can be performed, but uncorrectable bit error rates increase due to cell-to-cell interference

Engineering Contradiction:
Improveread accuracyVSAvoidcell-to-cell interference
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent applies parameter changes by dynamically adjusting read trim sets based on the programming status of neighboring cells. When a superblock is partially written, the system identifies which pages have been programmed and modifies read voltage parameters accordingly. This allows the read operation to compensate for cell-to-cell interference by using appropriate trim values that account for the presence or absence of programmed neighboring cells, thereby reducing uncorrectable bit errors.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If read trim sets are adjusted for all superblocks, then bit error rates are reduced, but controller complexity increases

Engineering Contradiction:
Improvebit error rateVSAvoidcontroller complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent implements local quality by applying different read trim sets selectively based on the local programming status of each superblock. Rather than uniformly adjusting trim sets across all superblocks, the system identifies specifically which superblocks are partially written and applies customized trim adjustments only to those cases. This selective approach reduces bit error rates where needed while avoiding unnecessary complexity in the controller logic for fully written superblocks.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The system employs self-service mechanisms by maintaining internal tracking of superblock programming status and automatically selecting appropriate read trim sets without requiring external intervention. The controller monitors which pages have been programmed in each superblock and autonomously determines the correct trim configuration, reducing the burden on external systems while managing the complexity internally through efficient status tracking.

Inventive Principle:
Principle #25Self-service

3Productivity

If multiple read trim sets are maintained, then read performance is improved, but memory resource requirements increase

Engineering Contradiction:
Improveread performanceVSAvoidmemory resources
Core Design Contradiction:
ProductivityVSQuantity of substance

Solution Approach 1:

The patent manages memory resources efficiently by dynamically changing read parameters (trim sets) based on the programming status of superblocks. Instead of permanently storing multiple complete read configurations, the system maintains a compact representation of superblock status and derives the appropriate trim set on-demand. This allows multiple read trim sets to be effectively utilized for improved read performance while minimizing the actual memory resources required to store and manage these parameters.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS10949291B2Partially written superblock treatment
Publication Date: 2021.03.16 MICRON TECHNOLOGY INC
  • US10949291B2 patent drawing
  • US10949291B2 patent drawing
  • US10949291B2 patent drawing

AI summary

The present disclosure relates to partially written superblock treatment. An example apparatus includes a memory device operable as a multiplane memory resource including blocks organized as superblocks. The memory device is configured to maintain, internal to the memory device, included in a status of an open superblock, a page indicator corresponding to a last written page of the open superblock. The memory device is further configured, responsive to receipt, from a controller, of a read request to a page of the open superblock, determine from page map information maintained internal to the memory device and from the indicator of the last written page, which of a number of different read trim sets to use to read the page of the open superblock corresponding to the read request.