Operand Collector Architecture for Multi-Ported Memory Simulation
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Solution Overview
Problem
Current data processing systems using single ported memories are inefficient compared to multi-ported memories, requiring more die area and power while reducing performance due to the need for multiple clock cycles to acquire operands for program instructions.
Innovation Solution
Simulating a multi-ported memory using lower port count memories by allocating memory banks and employing a collector unit to gather source operands from multiple banks, reducing die area and power consumption while maintaining performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a multi-ported memory is used to store operands, then the speed of acquiring operands is improved, but the die area and power consumption increase
Solution Approach 1:
The register file is divided into multiple banks, each bank being a separate memory unit. Multiple banks allow parallel access to different operands simultaneously, achieving multi-ported functionality while each bank remains a simpler single-ported memory structure, thus reducing overall die area compared to a true multi-ported memory.
Solution Approach 2:
Each memory bank is designed to be universally accessible through the collector unit, which can gather operands from any bank. This multi-functional approach allows the same bank structure to serve multiple purposes (storing different operands) while maintaining efficient access patterns that simulate multi-ported behavior.
2Speed
If a multi-ported memory is used to store operands, then the speed of acquiring operands is improved, but the power consumption increases
Solution Approach 1:
By segmenting the register file into multiple independent banks, the system achieves parallel operand access (improving speed) while each bank consumes less power individually. The total power consumption is lower than a single multi-ported memory because each bank can be accessed independently and efficiently, reducing overall energy usage.
Solution Approach 2:
The collector unit is pre-configured to gather operands from multiple banks in parallel before executing instructions. This preliminary gathering action ensures that all required operands are ready simultaneously, achieving high-speed access without the continuous high power consumption that would be required by a traditional multi-ported memory structure.
3Area of stationary object
If a single ported memory is used to store operands, then the die area and power consumption are reduced, but the productivity decreases due to multiple clock cycles needed
Solution Approach 1:
The register file is segmented into multiple banks that can be accessed in parallel. This segmentation allows the system to maintain simple single-ported memory structures (saving die area) while achieving multi-operand access capability through parallel bank access, thus maintaining high instruction execution throughput without requiring multiple sequential clock cycles.
Solution Approach 2:
The collector unit continuously gathers operands from multiple banks in parallel during each clock cycle, ensuring that useful action (operand acquisition) continues without interruption. This continuous parallel access maintains high productivity while using simple single-ported memory banks that require less die area compared to traditional multi-ported memories.
Data Source
AI summary
An apparatus and method for simulating a multi-ported memory using lower port count memories as banks. A collector units gather source operands from the banks as needed to process program instructions. The collector units also gather constants that are used as operands. When all of the source operands needed to process a program instruction have been gathered, a collector unit outputs the source operands to an execution unit while avoiding writeback conflicts to registers specified by the program instruction that may be accessed by other execution units.