Operand Dependency Tracking for Register Pair Instructions
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Solution Overview
Problem
Modern out-of-order microprocessor implementations only support tracking of three source registers per instruction, which is insufficient for correct execution of two-operand quad instructions operating on register pairs, leading to issues with operand dependency and increased latency.
Innovation Solution
Inserting a move instruction in the instruction scheduling dependency graph ensures operand readiness for all operands used by instructions operating on register pairs, eliminating the need for scratch registers and subsequent copy instructions, thereby reducing overhead and latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional out-of-order execution tracking is used for three source registers, then implementation complexity is reduced, but it cannot correctly execute two-operand quad instructions operating on register pairs
Solution Approach 1:
The patent segments the quad instruction into two separate internal instructions (instr1 and instr2), each operating on individual register pairs. This segmentation allows the existing three-source-register tracking mechanism to be applied to each segmented instruction, while the move instruction bridges the segmentation to maintain original instruction semantics
Solution Approach 2:
The patent introduces a move instruction as an intermediary element in the dependency graph. This move instruction acts as a mediator that connects the two segmented internal instructions, ensuring that operand dependencies are properly tracked and that both instr1 and instr2 receive their operands in synchronization without requiring complex four-source-register tracking
2Productivity
If internal instructions are issued independently without synchronization, then issue logic complexity is reduced, but operands may not be simultaneously available causing execution errors
Solution Approach 1:
The patent implements a feedback mechanism through the move instruction in the dependency graph. The move instruction creates a dependency loop that provides feedback to the issue logic, ensuring that instr1 and instr2 are only issued when their operands are simultaneously ready. This feedback ensures reliability while maintaining high productivity through out-of-order execution of other independent instructions
3Reliability
If scratch registers and copy instructions are used to handle operand dependencies, then operand readiness is ensured, but chip area and latency increase
Solution Approach 1:
The patent enables the instruction scheduling system to self-manage operand dependencies through the move instruction mechanism. Instead of requiring external scratch registers and copy instructions, the system uses the move instruction embedded in the dependency graph to automatically ensure operand readiness, thereby eliminating the need for additional chip area while maintaining reliability
Data Source
AI summary
A computer processing system is provided. The computer processing system includes a processor configured to insert a move instruction in an instruction scheduling dependency graph generated for operands of the instruction operating on register pairs to ensure operand readiness for all of the operands used by the instruction operating on register pairs.