Operand Size Control via Dirty Flag Register Flushing
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Solution Overview
Problem
Data processing systems face challenges in distinguishing between 32-bit and 64-bit operands during arithmetic and logical operations, leading to potential security vulnerabilities when switching between exception levels, as residual data from higher privilege levels can be accessed at lower privilege levels, compromising security.
Innovation Solution
The system employs 2N-bit registers and an instruction decoder that decodes an operand size field within arithmetic and logical instructions to specify operand sizes, allowing for controlled processing operations and using a dirty flag to manage register flushing during privilege level changes, ensuring secure data handling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If residual data in unallocated registers is not flushed when switching exception levels, then productivity is improved by avoiding unnecessary flushing operations, but security deteriorates as information leakage can occur between privilege levels
Solution Approach 1:
The patent applies preliminary action by setting a dirty flag bit in advance when a register is allocated and written to at a higher exception level. This flag is set before the exception level switch occurs, allowing the system to quickly identify and flush only the necessary registers during the privilege level transition without requiring comprehensive flushing of all registers, thus maintaining both security and productivity
Solution Approach 2:
The patent applies local quality by introducing a per-register dirty flag bit that individually tracks the allocation and write status of each register. Instead of treating all registers uniformly, the system selectively identifies and flushes only those specific registers that contain residual data from higher privilege levels, optimizing the flushing operation locally rather than globally
2Reliability
If all registers are flushed when switching exception levels, then security is improved by preventing information leakage, but productivity deteriorates due to increased flushing overhead
Solution Approach 1:
The patent applies the extraction principle by separating the identification of dirty registers from the flushing operation itself. The dirty flag bit extracts and marks only the specific registers that contain residual data, allowing the flushing mechanism to target only these identified registers rather than indiscriminately flushing all registers, thus reducing unnecessary flushing overhead while maintaining security
3Adaptability or versatility
If operand size field is included in all arithmetic and logical instructions, then adaptability is improved by enabling precise control of processing operations, but device complexity increases due to additional instruction decoding requirements
Solution Approach 1:
The patent applies universality by designing the operand size field to serve multiple functions across different instruction types. The same field configuration (e.g., W=1) universally indicates 32-bit operand processing for both arithmetic and logical instructions, while W=0 indicates 64-bit processing. This multi-functional approach allows a single decoding mechanism to handle various instruction types without requiring type-specific decoding logic, thereby reducing overall device complexity while maintaining adaptability
Data Source
AI summary
A data processing system is provided with processing circuitry as well as a bank of 64-bit registers. An instruction decoder decodes arithmetic instructions and logical instruction specifying arithmetic operations and logical operations to be performed upon operands stored within the 64-bit registers. The instruction decoder is responsive to an operand size field SF within the arithmetic instructions and the logical instructions specifying whether the operands are 64-bit operands or 32-bit operands where all of the operands are 64-bit operands or all of the operands are 32-bit operands. If a switch is made to a lower exception level, then a check is made as to whether or not a register being used was previously subject to a 64-bit write to that register. If such a 64-bit write had previously taken place, then the upper 32-bits are flushed so as to avoid data leakage from the higher exception level.