Operation Unit Graph Sorting for Reconfigurable Processor Placement
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Solution Overview
Problem
Traditional compilers and architectures struggle to efficiently implement massively parallel computations required for machine learning and artificial intelligence applications on reconfigurable processors, particularly coarse-grained reconfigurable architectures (CGRAs), as they lack effective methods for optimizing hardware resource allocation and data routing in dataflow graphs.
Innovation Solution
A sorting tool and cost estimation tool are used to determine an ordered sequence of nodes in an operation unit graph for placement and routing on a reconfigurable processor, optimizing performance by minimizing wire congestion, latency, and maximizing throughput.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional compilers and architectures are used to implement computations on reconfigurable processors, then implementation is simpler, but computational efficiency and resource allocation optimization are insufficient
Solution Approach 1:
The sorting tool determines an ordered sequence of nodes in the operation unit graph before placement and routing. This preliminary ordering based on cost estimation enables the placement tool to assign nodes to processing elements in an optimized sequence, minimizing wire congestion and latency without requiring complex post-placement optimization algorithms
2Loss of time
If nodes in operation unit graph are placed without optimized sequencing, then placement process is simpler, but wire congestion and latency increase
Solution Approach 1:
The sorting tool performs node sequencing before placement by estimating costs associated with placing each node at different positions. This preliminary cost-based ordering ensures that nodes are placed in an sequence that minimizes wire congestion and latency, avoiding the need for complex iterative optimization during placement
Solution Approach 2:
The cost estimation tool provides feedback about the cost of placing nodes at different positions based on current placement state. This feedback mechanism allows the sorting tool to determine an ordered sequence that anticipates and minimizes future wire congestion and latency issues
3Productivity
If cost estimation and sorting tools are used to determine node sequence, then wire congestion and latency are minimized, but computational overhead increases
Solution Approach 1:
The cost estimation and sorting operations are performed once before placement, establishing an optimized node sequence that guides the placement process. This preliminary optimization achieves high data throughput without requiring continuous complex computations during runtime, reducing overall computational overhead
Data Source
AI summary
The present application describes a method of operating a compiler that is executable in one or more processors coupled to a storage medium. The method comprises receiving an operation unit graph comprising a set of unsorted nodes and edges that interconnect nodes in the set of unsorted nodes, determining an ordered sequence of nodes from the set of unsorted nodes, receiving a hardware description describing a reconfigurable processor, and using the hardware description to determine an assignment of the nodes of the ordered sequence of nodes in order of the ordered sequence of nodes onto the reconfigurable processor during placement of the operation unit graph.