Operation Module Extension Instruction for Sparse Vector Processing
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Solution Overview
Problem
Existing vector operation instructions cannot perform variable-scale or sparse vector/matrix operations, leading to higher computational overhead and energy consumption, especially in sparse neural networks where operations on sparse data are required.
Innovation Solution
An operation module and method that utilize an extension instruction with an opcode and opcode domain to execute multiple operations using a single instruction, including input data addressing, indexing, and data types, allowing for conversion and execution of operations on sparse data in various indexing modes, reducing the need for intermediate results storage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If existing vector operation instructions are used, then fixed-size vector operations can be performed, but variable-scale and sparse vector/matrix operations cannot be implemented
Solution Approach 1:
The patent introduces dynamic parameters including variable vector length N and sparsity indication bit k into the instruction format. The extension instruction dynamically adapts to different operation scales and data sparsity levels, allowing the same instruction to handle both dense and sparse operations with varying dimensions without requiring multiple fixed-size instruction variants.
Solution Approach 2:
The extension instruction serves multiple functions: it performs both dense and sparse vector/matrix operations, supports variable scaling, and handles different data types (floating-point and fixed-point). By integrating sparsity indication bit k and variable length parameter N into the instruction, a single instruction format achieves what previously required multiple specialized instructions.
2Productivity
If multiple separate instructions are used for different operations, then operation specificity is maintained, but computational overhead and energy consumption increase
Solution Approach 1:
The patent merges multiple operation types (addition, multiplication, activation functions) and data format handling (dense/sparse, different precisions) into a single extension instruction. This consolidation eliminates the need for separate instruction sequences for each operation type, reducing both computational overhead and energy consumption while maintaining operational specificity through the opcode field.
Solution Approach 2:
The extension instruction achieves multi-functionality by incorporating operation type identification (opcode), variable length specification (N), and sparsity indication (k) into a unified instruction format. This allows the processor to execute diverse operations efficiently without the overhead of multiple specialized instruction pipelines.
3Reliability
If intermediate results are stored for multi-step operations, then operation accuracy is maintained, but storage space and read/write overhead increase
Solution Approach 1:
The extension instruction performs preliminary setup by encoding all necessary operation parameters (length N, sparsity k, operation type) within the instruction itself. This allows the processor to configure the operation pipeline in advance without requiring intermediate storage of operational metadata, reducing memory access overhead while maintaining operational precision.
Data Source
AI summary
There is provides an operation module, which includes a memory, a register unit, a dependency relationship processing unit, an operation unit, and a control unit. The memory is configured to store a vector, the register unit is configured to store an extension instruction, and the control unit is configured to acquire and parse the extension instruction, so as to obtain a first operation instruction and a second operation instruction. An execution sequence of the first operation instruction and the second operation instruction can be determined, and an input vector of the first operation instruction can be read from the memory. The operation unit is configured to convert an expression mode of the input data index of the first operation instruction and to screen data, and to execute the first and second operation instruction according to the execution sequence, so as to obtain an extension instruction.