Operator-Aware FSM for Circuit Simulation Resource Optimization
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Solution Overview
Problem
Existing methods for modeling SystemVerilog assertion sequences are inefficient in terms of memory and computational resource usage due to challenges with temporal operators and composite operators, leading to costly simulations and delayed product releases.
Innovation Solution
The approach involves using operator-aware states, transient states, and thread merging in finite state machines (FSMs) to simulate circuit designs, where threads are forked and joined based on composite operators, and transient states allow for zero-delay transitions, reducing resource usage by merging identical threads.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional methods are used to model SystemVerilog assertion sequences, then the simulation can handle complex temporal operators and composite operators, but memory and computational resource usage increases significantly
Solution Approach 1:
The patent segments the assertion sequence evaluation into multiple finite state machines (FSMs), where each FSM handles a specific portion of the sequence. This segmentation allows complex assertions to be broken down into manageable state transitions, reducing the memory required to track the entire sequence in a single model while maintaining evaluation accuracy.
Solution Approach 2:
The patent merges multiple simulation threads that are evaluating identical or equivalent sequence portions into a single shared FSM evaluation. By detecting when multiple threads are pursuing the same assertion path, the system combines their evaluations, eliminating redundant computations and reducing overall memory consumption while preserving simulation reliability.
2Reliability
If traditional methods are used to model SystemVerilog assertion sequences, then the simulation can handle complex temporal operators and composite operators, but computational resource usage and runtime increase
Solution Approach 1:
The patent performs preliminary analysis of the assertion sequence to identify common sub-sequences and equivalent evaluation paths before simulation begins. This pre-processing allows the creation of a shared FSM structure that multiple threads can utilize, avoiding redundant evaluation work during simulation and significantly improving computational efficiency while maintaining accuracy.
Solution Approach 2:
Instead of creating separate complete FSM copies for each simulation thread, the patent creates a single shared FSM that can be referenced by multiple threads. This eliminates the need to copy entire state machine structures, reducing memory allocation overhead and improving simulation speed while preserving the ability to handle complex temporal and composite operators.
3Ease of operation
If separate FSM instances are created for each simulation thread, then each thread can independently evaluate assertion sequences, but memory consumption increases due to duplicate state machine structures
Solution Approach 1:
The patent creates a universal FSM structure that can serve multiple simulation threads simultaneously. This single FSM is designed to handle evaluation requests from any thread, making it multi-functional. The FSM maintains thread independence through proper state management while eliminating the need for duplicate instances, thereby reducing memory consumption without compromising operational independence.
Solution Approach 2:
The patent introduces an intermediary mechanism that manages shared FSM access between multiple threads. This intermediary coordinates thread requests to the shared FSM, ensuring thread-safe operation and maintaining the appearance of independent evaluation while actually utilizing a common resource. This approach reduces memory consumption by eliminating duplicates while preserving thread independence through controlled access.
Data Source
AI summary
Disclosed approaches involve simulating a circuit design specified in a hardware description language (HDL). During simulation, a thread is started at an edge of a simulation clock signal for evaluation of states of a finite state machine (FSM) that represent a series of events specified in a statement in the HDL. The thread transitions from one state to a next state in the FSM in response to evaluation of the one state. In response to encountering a fork state in the FSM, the thread is forked into two threads during simulation. The fork state represents a composite operator in the statement, and the FSM has a branch from the fork state for each operand of the composite operator. In response to encountering a join state in the FSM by the two threads, the two threads are joined into one thread.