OPMISR++ PRPG Control Rotation for Scan Data Interdependence
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current scan data testing methods for integrated circuits are inefficient due to high test time, large data volumes, and data interdependence issues, particularly in ASIC and processor chips, which hinder fault detection and increase test coverage requirements.
Innovation Solution
The implementation of an enhanced scan data testing method using On Product Multiple Input Signature Register (OPMISR++) with a Pseudo-Random Pattern Generator (PRPG) and control rotation, which breaks data interdependence by distributing unique PRPG control data from a 32-bit scan bus to all logic sections, allowing for reduced test data volume and increased test coverage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If scan data is compressed using OPMISR with fan-out network, then data volume is reduced, but data interdependence between channels increases making some logic untestable
Solution Approach 1:
The patent divides the scan data into two independent parts: 4 control bits that are distributed to all chiplets through the fan-out network, and 28 data bits that are uniquely assigned to each chiplet through the stump mux structure. This segmentation allows each chiplet to receive unique test data while still benefiting from the compressed 4-bit control signal, thereby reducing data interdependence and maintaining test coverage.
Solution Approach 2:
The patent applies different data distribution strategies to different parts of the chiplet structure. The control bits (0-3) are universally distributed to all chiplets, while the data bits (4-31) are locally assigned to specific chiplets. This local quality differentiation ensures that each chiplet receives tailored test data that maximizes fault detection capability for that specific chiplet region.
2Reliability
If traditional scan testing is applied to large ASIC chips, then comprehensive test coverage is achieved, but test time and data volume increase significantly
Solution Approach 1:
The patent merges multiple test functions into a single compressed 4-bit control signal that can be simultaneously applied to all chiplets through the fan-out network. By combining the control and data functions into this unified signal structure, the system achieves comprehensive test coverage across all chiplets in parallel, dramatically reducing the total test time compared to traditional sequential scanning methods.
Solution Approach 2:
The 4-bit control signal serves multiple functions simultaneously: it acts as both the test pattern generator and the chiplet selection signal, and can be universally applied to all chiplets in the array. This multi-functionality allows a single test signal to perform multiple testing operations across different chiplet regions, reducing the overall test time while maintaining comprehensive coverage.
3Quantity of substance
If PRPG is used to generate scan patterns, then test data volume is reduced, but the ability to target specific faults deterministically is limited
Solution Approach 1:
The patent introduces dynamic control over the PRPG through the 4-bit control signal that can be independently adjusted for each chiplet. This dynamic control mechanism allows the test patterns to be adaptively modified based on the specific fault locations and characteristics, enabling deterministic fault targeting while maintaining the space-efficient PRPG structure.
Solution Approach 2:
The patent changes the parameters of the PRPG output by using the 4-bit control signal to select and rotate different portions of the 32-bit scan bus (0-3, 4-7, 8-11, or 12-15). This parameter transformation allows the same PRPG structure to generate different test patterns tailored to specific fault locations, providing both compact data volume and targeted fault detection capability.
Data Source
AI summary
A method and circuit are provided for implementing enhanced scan data testing for test time reduction and decreased scan data interdependence with on product multiple input signature register (OPMISR++) testing, and a design structure on which the subject circuit resides. A respective Pseudo-Random Pattern Generator (PRPG) provides channel input patterns to a respective associated scan channel used for the OPMISR++ diagnostics. Control inputs are coupled to the Pseudo-Random Pattern Generator (PRPG) providing PRPG control distribution. The PRPG selectively provides controlled channel input patterns for the respective scan channel responsive to the control inputs.