Semiconductor Package with Opposing Leadframe Die Mounting
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Solution Overview
Problem
Existing semiconductor packages for synchronous buck converters often require clip layers for vertical stacking, leading to increased size and manufacturing costs, as well as higher parasitic inductance due to wire bonds, which affects power efficiency and heat dissipation.
Innovation Solution
A semiconductor package design featuring a first die in a flipchip arrangement on one surface of a leadframe and a second die connected via wire bonds on the opposing surface, eliminating the need for clip layers and allowing for a compact, low-impedance connection between dies, thereby reducing package size and manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wire bonds are used to connect dies to leads, then electrical connections are provided, but parasitic inductance increases significantly
Solution Approach 1:
The patent extracts and eliminates the wire bonds from the power circuit path. Instead of using wire bonds to connect dies to leads, the invention directly connects the power MOSFET dies to the leadframe leads through solder joints, removing the source of parasitic inductance from the critical power switching path.
Solution Approach 2:
The leadframe itself serves as an intermediary that provides both mechanical support and electrical connection. The leads are directly soldered to the die pads, creating a low-inductance path that eliminates the need for separate wire bond intermediaries in the power circuit.
2Object-generated harmful factors
If clips are used to substitute for wire bonds, then parasitic inductance is reduced, but device complexity and manufacturing complexity increase
Solution Approach 1:
The patent removes the clip layer entirely from the assembly. By directly soldering the power MOSFET dies to the leadframe leads, the invention eliminates the need for clips that would otherwise be required to provide mechanical support and electrical connection in stacked configurations.
Solution Approach 2:
The invention merges the functions of mechanical support and electrical connection into a single integrated structure. The leadframe leads serve both as structural elements and as electrical conductors, eliminating the need for separate clip components.
3Reliability
If dies are stacked vertically with clips, then connection to switch node is achieved, but package size increases
Solution Approach 1:
The patent extracts and removes the clip layer that would be required to support vertically stacked dies. By directly soldering dies to the leadframe leads, the invention achieves switch node connection without the additional height and volume required for clips.
Solution Approach 2:
The invention transitions from a vertical stacking architecture requiring clips to a planar arrangement where dies are mounted on the same side of the leadframe. This dimensional reorganization eliminates the need for vertical support structures and reduces overall package height.
4Reliability
If multiple wire bonds are used for die connections, then electrical connectivity is achieved, but manufacturing cost increases
Solution Approach 1:
The patent removes wire bonds from the manufacturing process entirely. By using direct solder joint connections between dies and leadframe leads, the invention eliminates the costly wire bonding step while maintaining electrical connectivity.
Solution Approach 2:
The invention replaces the mechanical wire bonding process with a thermal soldering process. Solder joints are formed through reflow processing, which is generally more cost-effective and better suited for automated manufacturing than precision wire bonding.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration results in smaller packages with reduced manufacturing costs, lower impedance connections, improved power efficiency, and enhanced heat dissipation, supporting efficient operation of synchronous buck converters.
Implementation Method 1
the source of sync FET 130 is soldered to leadframe pad 111 by solder layer 131
Implementation Method 2
wire bonds electrically connecting the second semiconductor die to the leadframe
Implementation Method 3
mold compound at least partially covering the first semiconductor die, the second semiconductor die and the wire bonds
Data Source
AI summary
A package includes a leadframe having first surface and a second surface opposing the first surface, the leadframe forming a plurality of leads, a first semiconductor die mounted on the first surface of the leadframe and electrically connected to at least one of the plurality of leads, a second semiconductor die mounted on the second surface of the leadframe, wire bonds electrically connecting the second semiconductor die to the leadframe, and mold compound at least partially covering the first semiconductor die, the second semiconductor die and the wire bonds.