Opposite Die Orientation in Power Modules to Cancel Parasitic Inductance
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Solution Overview
Problem
Power semiconductor devices face voltage spikes and over-voltages due to parasitic inductances in wire bonds, which can lead to device destruction, and current interruption, despite the use of decoupling capacitors and snubbers, which increase manufacturing costs and consume space and energy.
Innovation Solution
The use of power semiconductor modules with die assembled in opposite orientations to reduce parasitic impedances, allowing for interconnect configurations that minimize voltage spikes and over-voltages, eliminating the need for snubbers and enabling on-die decoupling capacitors and double-sided cooling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If wire bonds are used to connect terminals of power semiconductor devices to lead frame, then electrical interconnects are established, but parasitic inductances are introduced that cause voltage spikes and over-voltages
Solution Approach 1:
The patent inverts the conventional die orientation arrangement by mounting opposite-type devices (e.g., IGBT and diode) in opposite orientations on the substrate. This inversion allows the formation of opposing current loops that generate opposing magnetic fields, which cancel each other's parasitic inductance effects, thereby eliminating voltage spikes without complicating the manufacturing process
Solution Approach 2:
The patent converts the harmful parasitic inductance effect into a beneficial cancellation mechanism. By deliberately arranging current paths to create opposing magnetic fields through inverted die orientations, the harmful inductive voltage spikes are transformed into a self-cancelling phenomenon where the magnetic fields neutralize each other, turning a defect into a solution
2Object-affected harmful factors
If decoupling capacitors are incorporated into circuits to mitigate noise from parasitic inductances, then voltage spike protection is improved, but manufacturing cost and device complexity increase
Solution Approach 1:
The patent extracts and eliminates the root cause of voltage spikes (parasitic inductances) through inverted die orientation arrangement, making additional protective components like decoupling capacitors unnecessary. By removing the source of the problem rather than adding protective measures, the solution reduces device complexity while maintaining protection against voltage spikes
3Reliability
If snubbers are used to protect power semiconductor devices from over-voltages, then device reliability is improved, but manufacturing cost and space consumption increase
Solution Approach 1:
The patent removes the need for snubber circuits by extracting and eliminating the parasitic inductance problem at its source through inverted die orientation. This inherent design protection eliminates the requirement for additional snubber components, maintaining device reliability while reducing overall device complexity and component count
Solution Approach 2:
The patent implements a self-service protection mechanism where the inverted die orientation arrangement creates self-cancelling magnetic fields that automatically protect against over-voltages. This self-protection mechanism eliminates the need for external snubber components, as the device structure itself provides the necessary protection through its geometric arrangement
4Power
If multiple modules are used to increase power density, then power output is improved, but parasitic inductances and voltage spikes increase
Solution Approach 1:
The patent applies inverted die orientation arrangement within each module to create opposing current loops that cancel parasitic inductance effects. This allows multiple modules to be combined to increase power density while each module's inverted configuration prevents the accumulation of voltage spikes, enabling high-power applications without proportionally increasing harmful electromagnetic effects
Data Source
AI summary
An electronic apparatus includes a base substrate, the base substrate including an interconnect. The electronic apparatus further includes a first die including a first semiconductor device, the first semiconductor device being coupled to the interconnect, and further includes a second die including a second semiconductor device, the second semiconductor device being coupled to the interconnect. The first and second die are attached to the base substrate in opposite orientations.


