Opposite-Side p-Type and n-Type CFETs for Thermal Damage Control
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Solution Overview
Problem
The challenge of forming reliable semiconductor devices at smaller sizes is exacerbated by the increasing complexity and difficulty of fabrication processes as feature sizes continue to decrease, affecting the quality and reliability of transistors.
Innovation Solution
A complementary FET (CFET) structure is developed with p-type and n-type transistors formed on opposite sides of a dielectric layer, utilizing high-quality crystalline semiconductor layers and semiconductive oxide channels, allowing for separate processing conditions to enhance transistor quality and durability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If transistors are formed on the same side of a dielectric layer, then processing can be performed in a single location, but thermal damage occurs to the first transistor during formation of the second transistor
Solution Approach 1:
The patent divides the transistor formation process into two separate locations (first side and second side of the dielectric layer) to prevent thermal damage. The first transistor is formed on a first side of the dielectric layer, then the dielectric layer is flipped over to expose a second side where the second transistor is formed. This segmentation allows independent processing conditions for each transistor, resolving the contradiction between processing convenience and transistor quality.
Solution Approach 2:
The patent employs inversion by flipping the dielectric layer over after forming the first transistor. This allows the second transistor to be formed on the opposite side under different processing conditions, preventing thermal damage to the first transistor while maintaining manufacturing feasibility.
2Productivity
If feature sizes are decreased to increase functional density, then production efficiency improves, but fabrication process complexity and difficulty increase
Solution Approach 1:
The patent transitions from planar transistor formation to three-dimensional formation by utilizing both sides of the dielectric layer. This dimensional change allows increased functional density without proportionally increasing fabrication complexity, as the same processing steps can be applied to both sides of the flipped dielectric layer.
Data Source
AI summary
A semiconductor device includes a dielectric layer, a p-type transistor over a first side of the dielectric layer, and an n-type transistor over a second side of the dielectric layer opposite to the first side of the dielectric layer. The p-type transistor includes a semiconductor channel layer, a first gate structure over the semiconductor channel layer, and source/drain epitaxy structures on opposite sides of the first gate structure. The n-type transistor includes a semiconductive oxide channel layer, a second gate structure over the semiconductive oxide channel layer, and source/drain contacts on opposite sides of the second gate structure.