Optic Module Addressing via Transmit Disable Signal

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Solution Overview

Problem

In optic module configurations, the standard compliance requirement for identical addressing hinders efficient communication between a host and multiple modules within a single enclosure, as each module must be addressed in the same manner, leading to issues with shared bus communication and increased costs due to the need for separate hosts or manual intervention.

Innovation Solution

A method and apparatus that allow optic modules within a shared enclosure to be assigned unique addresses by using a two-line path and transmit disable signals, enabling selective communication and address reconfiguration, thereby allowing a single host to manage multiple modules efficiently.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If standard compliance addressing is used for optic modules, then standard compatibility is maintained, but communication efficiency between host and multiple modules deteriorates

Engineering Contradiction:
Improvestandard complianceVSAvoidcommunication efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent changes the addressing parameter from fixed standard-compliant addresses to dynamically assignable unique addresses. Each module's address is modified based on its identifier and the host's assignment, allowing efficient selective addressing while maintaining standard compliance in the communication protocol itself

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The addressing scheme transitions from static standard addresses to dynamic unique addresses that can be assigned and reassigned by the host. This dynamic addressing allows the system to adapt to different module configurations and enables efficient communication without requiring separate hosts

Inventive Principle:
Principle #15Dynamics

2Ease of operation

If separate hosts are used for each optic module, then unique addressing is achieved, but system cost and complexity increase

Engineering Contradiction:
Improveunique addressing capabilityVSAvoidnumber of hosts required
Core Design Contradiction:
Ease of operationVSDevice complexity

Solution Approach 1:

The patent merges multiple module control functions into a single shared host. By implementing unique addressing at the module level through identifier-based addressing, multiple modules can be controlled through one host without requiring separate host devices for each module

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The module identifier acts as an intermediary that enables unique addressing without requiring separate hosts. The identifier serves as a mediator between the shared host and individual modules, allowing the host to selectively address and control specific modules through the two-wire interface

Inventive Principle:
Principle #24Intermediary (Mediator)

3Ease of operation

If manual intervention is used to switch between modules, then unique module selection is possible, but operational efficiency and time consumption deteriorate

Engineering Contradiction:
Improvemodule selection capabilityVSAvoidtime for module switching
Core Design Contradiction:
Ease of operationVSLoss of time

Solution Approach 1:

The system implements self-service automatic module selection through unique addressing. Instead of requiring manual intervention to switch between modules, the host can automatically select and communicate with specific modules based on their unique addresses derived from identifiers, enabling rapid automated module selection and control

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS7721012B2Reprogrammable device address for a serial interface in an optic module
Publication Date: 2010.05.18 MACOM TECH SOLUTIONS HLDG INC
  • US7721012B2 patent drawing
  • US7721012B2 patent drawing
  • US7721012B2 patent drawing

AI summary

An optic module is disclosed having a shared bus interface, a transmit disable line, a memory and control logic or a processor configured to facilitate address modification via a bus shared by multiple optic modules. A single housing may contain multiple modules, all of which are preferably accessible via a shared host via a shared bus. Standard compliant modules share a common address, which inhibits communication with only a particular optic module, via the shared bus, in a housing containing multiple optic modules. Using a common message to all modules to treat a transmit disable line as a module select line, a single module may be active during an address re-write operation. This process may repeat until all the modules within the housing have unique addresses.