Optical Amplifier FPGA Update Latch Mechanism

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Solution Overview

Problem

Updating the FPGA in an optical amplifying apparatus during operation interrupts control of optical signals, causing communication failures and requiring time-consuming parameter rewriting, while using two FPGAs is costly and large in size.

Innovation Solution

Incorporating a latch unit between the gate array and circuits to temporarily store parameters and control devices using these stored parameters, allowing continuous optical amplification and easy parameter reproduction during updates, without the need for additional FPGAs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If the FPGA is updated during operation, then the FPGA can be improved or updated with new programs, but control of optical signals is interrupted causing communication failure

Engineering Contradiction:
ImproveFPGA program update capabilityVSAvoidoptical signal control continuity
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The system performs preliminary actions by storing control parameters in the latch unit before FPGA update begins. The latch unit holds the driving current parameters and temperature parameters that will be needed after update, ensuring control continuity without interruption to optical signal processing.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The latch unit acts as an intermediary between the FPGA and the control circuits. During FPGA update, the latch unit mediates by providing stored parameters to the control circuits, preventing direct interruption of control signals while the FPGA is being reprogrammed.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Adaptability or versatility

If the FPGA parameters are rewritten after updating, then the FPGA can function with new parameters, but it takes a lot of time and effort

Engineering Contradiction:
ImproveFPGA parameter updateVSAvoidparameter rewriting time
Core Design Contradiction:
Adaptability or versatilityVSLoss of time

Solution Approach 1:

The latch unit pre-stores the necessary control parameters before FPGA update occurs. This preliminary storage action eliminates the need for time-consuming parameter rewriting after update, as parameters are already prepared and available in the latch unit for immediate use.

Inventive Principle:
Principle #10Preliminary action

3Reliability

If two FPGAs are used for backup and update, then control can continue during update, but the system becomes large-sized and expensive

Engineering Contradiction:
Improvecontrol continuity during updateVSAvoidnumber of FPGAs
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The invention extracts the parameter storage function from the FPGA itself and places it in a separate latch unit. This allows a single FPGA to be used for control while its parameters are independently stored and preserved in the latch unit, eliminating the need for a second backup FPGA.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The latch unit serves multiple functions: it stores control parameters during normal operation, preserves parameters during FPGA update, and provides parameters to control circuits after update. This multi-functional component replaces the need for a dedicated backup FPGA.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS7852550B2Optical amplifying apparatus
Publication Date: 2010.12.14 MOLEX INC
  • US7852550B2 patent drawing
  • US7852550B2 patent drawing
  • US7852550B2 patent drawing

AI summary

The present invention provides an optical amplifying apparatus having: a CPU 11 for processing various signals; a plurality of circuits 17, 18 for controlling respective devices 4, 9 required for optical amplification; a first storing unit 14 for storing a program supplied from a user a gate array 12 for storing various parameters for controlling the devices 4, 9, the gate array being updated based on the program which is stored in the first storing unit 14 and sent via the CPU 11; a latch unit 13, provided between the gate array 12 and the circuits 17, 18, for interrupting a signal path from the gate array 12 to the circuits 17, 18 after receiving a starting signal of an update from the CPU 11 until the update being finished and for controlling the circuits 17, 18 based on the parameters stored in the gate array 12 before the signal path is interrupted; and a second storing unit 16 for, at least during the update, storing the various parameters which are stored in the gate array 12 before the update.