Optical Burst Transport Network Timeslot Synchronization Without Fiber Delay Lines

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Solution Overview

Problem

Current optical burst switching networks require Fiber Delay Lines (FDLs) for timeslot synchronization, leading to complex network design, tedious length control, and optical power losses, making it impractical to achieve precise timeslot synchronization.

Innovation Solution

A method for implementing timeslot synchronization in an Optical Burst Transport Network (OBTN) that eliminates the need for FDLs by using a master node to detect network topology, calculate timeslot length, and perform synchronization training, thereby simplifying node design and improving time precision without optical efficiency loss.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If Fiber Delay Lines (FDLs) are configured for timeslot synchronization in optical burst switching networks, then timeslot synchronization can be achieved, but network design becomes complex and optical power is lost

Engineering Contradiction:
Improvetimeslot synchronization precisionVSAvoidnetwork design complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent extracts and eliminates the FDL component from the optical burst switching network. Instead of using FDLs for timeslot synchronization, the invention uses a master node to detect network topology and calculate timeslot lengths, thereby removing the complex FDL configuration while maintaining synchronization precision

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent replaces the mechanical/optical FDL delay mechanism with an electronic control mechanism. The master node uses detection and calculation algorithms to determine timeslot synchronization parameters, substituting the physical FDL delay line with a computational approach that avoids optical power loss and design complexity

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

2Measurement precision

If Fiber Delay Lines (FDLs) are configured for timeslot synchronization, then synchronization can be achieved, but optical power is lost

Engineering Contradiction:
Improvetimeslot synchronization precisionVSAvoidoptical power loss
Core Design Contradiction:
Measurement precisionVSLoss of energy

Solution Approach 1:

The patent removes the FDL component that causes optical power loss. By using master node detection and calculation instead of physical FDLs, the system achieves timeslot synchronization without the associated optical power attenuation

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent substitutes the optical FDL delay mechanism with an electronic control system. The master node calculates timeslot parameters and sends control signals to slave nodes, replacing the power-lossy optical delay with an efficient electronic computation and signaling approach

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

3Measurement precision

If FDL arrays are increased to improve time precision of timeslot synchronization, then synchronization precision improves, but the number of FDLs needed becomes unrealistic

Engineering Contradiction:
Improvetimeslot synchronization precisionVSAvoidnumber of FDLs
Core Design Contradiction:
Measurement precisionVSQuantity of substance

Solution Approach 1:

The patent extracts the FDL component entirely from the system architecture. Instead of scaling up the number of FDLs, the invention uses a master node that detects network topology and calculates optimal timeslot lengths, eliminating the need for multiple FDL arrays

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent introduces dynamic adaptation capability through the master node. The system can dynamically detect network topology changes and recalculate timeslot synchronization parameters, replacing the static FDL configuration approach with a flexible, adaptive computational method

Inventive Principle:
Principle #15Dynamics

Data Source

PatentEP3206314B1Method and device for implementing timeslot synchronization
Publication Date: 2024.03.13 ZTE CORP
  • EP3206314B1 patent drawingFigure 1
  • EP3206314B1 patent drawingFigure 2
  • EP3206314B1 patent drawingFigure 3(a)

AI summary

Provided are a method and a device for implementing timeslot synchronization. The method includes: a master node performing timeslot synchronization training of an OBTN according to a timeslot length of the OBTN. By adopting the solution provided by the embodiments of the present invention, an FDL does not need to be considered in node design, the node design is simplified, the time precision of synchronization is improved and no loss is caused to optical efficiency.