Optical Semiconductor Capacitor Layout for Low Parasitic Capacitance
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Solution Overview
Problem
The existing optical semiconductor devices face a challenge due to the increased parasitic capacity caused by a larger conductive pattern, which results in decreased amplitude response and lowered signal sensitivity at high frequencies.
Innovation Solution
The optical semiconductor device incorporates a submount with a first conductive pattern on its upper surface and a GND pattern on its lower surface, where the conductive pattern has a protruding portion narrower than the capacitor, allowing for appearance inspection of solder and reducing parasitic capacity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Difficulty of detecting and measuring
If the conductive pattern is made larger than the capacitor, then appearance inspection of solder is enabled, but parasitic capacity increases and signal sensitivity decreases
Solution Approach 1:
The conductive pattern is divided into two functional zones: a larger first conductive pattern for solder inspection and a narrower second conductive pattern for low-parasitic connections. This segmentation allows each zone to fulfill its specific function without compromising the other.
Solution Approach 2:
Different regions of the conductive pattern have different width characteristics. The first conductive pattern has a larger width for inspection purposes, while the second conductive pattern has a narrower width to minimize parasitic capacity. This local differentiation resolves the contradiction between inspection needs and signal quality.
2Ease of operation
If the conductive pattern is made larger, then solder wettability inspection is improved, but high frequency performance deteriorates
Solution Approach 1:
The conductive pattern is segmented into inspection-oriented and signal-oriented portions, allowing simultaneous achievement of ease of inspection and high frequency performance.
Solution Approach 2:
The conductive pattern exhibits local quality variation with wider regions for inspection and narrower regions for signal transmission, optimizing both inspection ease and high frequency performance in their respective zones.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables improved high-frequency performance by reducing noise and enhancing signal sensitivity, while still allowing for reliable appearance inspection of the solder.
Implementation Method 1
a capacitor having a lower surface electrode bonded to the first conductive pattern with solder
Data Source
AI summary
A first conductive pattern (13) is provided on an upper surface of the submount (7). A GND pattern (9) is provided on a lower surface of the submount (7). A lower surface electrode (21) of a capacitor (3) is bonded to the first conductive pattern (13) with solder (22). An upper surface electrode (23) of the capacitor (3) is connected to a light emitting device (2). A terminating resistor (4) is connected to the first conductive pattern (13). The first conductive pattern (13) has a protruding portion (25) which protrudes outside from the capacitor (3) in planar view. A width of the protruding portion (25) is narrower than a width of the capacitor (3).