Optical Chip Package Structure with Interposer and Through-Silicon-Via
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Solution Overview
Problem
Existing optical chip mounting configurations on substrates result in longer conductive paths, leading to increased parasitic capacitance and resistance, which limits operation frequency and increases power loss.
Innovation Solution
A package structure with a molded package encapsulating the optical chip, connected to a PCB substrate via an interposer with a through-silicon-via structure, reducing the conductive path length and omitting fabrication processes for bump structures on the interposer and molded package.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the optical chip is mounted directly on the substrate without a molded package structure, then the device complexity is reduced, but the conductive path length increases leading to higher parasitic capacitance and resistance
Solution Approach 1:
The optical chip is nested within a molded package structure that is itself mounted on the substrate, creating a hierarchical integration. This nested configuration allows the conductive path to be optimized within the package while maintaining overall device functionality, resolving the contradiction between structural simplicity and electrical performance.
Solution Approach 2:
A molded package structure with an interposer acts as an intermediary between the optical chip and the substrate. This intermediary component provides optimized conductive paths through through-silicon-via structures, reducing parasitic effects while maintaining a manageable device architecture.
2Reliability
If a molded package structure with interposer is used, then parasitic capacitance and resistance are reduced, but the manufacturing process complexity increases
Solution Approach 1:
The molded package structure and interposer are prepared in advance with pre-formed conductive paths and via structures. This preliminary preparation allows the optical chip to be mounted onto a pre-optimized platform, reducing the complexity of on-site fabrication while maintaining high electrical performance.
3Productivity
If the conductive path length is reduced through interposer with through-silicon-via, then operation frequency increases and power loss decreases, but the device complexity increases
Solution Approach 1:
The interposer introduces a vertical dimension to the conductive path through through-silicon-via structures, transforming the electrical connection from a planar layout to a three-dimensional configuration. This dimensional change shortens the effective conductive path length, enabling higher operation frequencies despite increased structural complexity.
Data Source
AI summary
An apparatus includes a package structure. The package structure includes a chip, a conductive structure over the chip, a molding structure surrounding and underneath the chip, and a first passivation layer over the conductive structure. The chip includes an optical component and a chip conductive pad. The conductive structure is electrically coupled to the chip conductive pad. The conductive structure has a planar portion substantially in parallel with an upper surface of the chip. The first passivation layer has a first opening defined therein. The first opening exposes a portion of the planar portion. The package structure is configured to receive an electrical coupling through the first opening in the first passivation layer.