Optical Chip Package Layout for Compact Multi-Chip Integration
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Solution Overview
Problem
Conventional packaging techniques for semiconductor chips, especially when incorporating optical functions, require enlarging the interposer substrate, leading to an increase in package size.
Innovation Solution
A package design that includes a plurality of chips with an optical chip, a wiring layer, and a molding material with a flattened surface surrounding the chips, where the optical chip is sealed and supported, and may include a transparent member and dummy chips to maintain chip uniformity and reduce mounting area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the interposer substrate is enlarged to accommodate additional chips or optical functions, then the functional versatility is improved, but the package size increases
Solution Approach 1:
The patent transitions from a two-dimensional planar arrangement to a three-dimensional stacked configuration. Multiple chips are vertically stacked and interconnected through through-electrodes, enabling functional expansion without increasing the horizontal footprint of the package. This vertical integration allows additional optical functions and chips to be incorporated while maintaining a compact package size.
Solution Approach 2:
The patent implements a nested structure where chips are stacked one on top of another, with each chip containing functional elements. The through-electrodes penetrate through multiple chip layers, creating a nested interconnection system. This nesting approach maximizes the use of vertical space, allowing multiple functional layers to be integrated within a small horizontal area, thus improving versatility without increasing package size.
2Adaptability or versatility
If the interposer substrate is enlarged to incorporate optical functions, then the optical functionality is improved, but the manufacturing complexity increases
Solution Approach 1:
The patent divides the optical functional elements into separate, modular chip components rather than integrating them into a single large interposer substrate. Each chip can be independently manufactured, tested, and optimized for specific optical functions. This segmentation reduces the complexity of the substrate design and allows for standardized interconnections through through-electrodes, simplifying the overall manufacturing process despite the increased functional capability.
3Adaptability or versatility
If chips of different sizes are mounted on the wiring layer, then the functional integration is improved, but the mounting uniformity deteriorates
Solution Approach 1:
The patent applies local quality by providing individual molding materials for each chip mounting region. Each molding material is customized to match the specific chip size and shape it covers, ensuring optimal protection and electrical isolation. This localized approach allows chips of different sizes to be mounted on the same wiring layer while maintaining uniform mounting precision, as each chip receives tailored support and encapsulation rather than relying on a single uniform structure.
Data Source
AI summary
It is possible to cope with expansion of functions while suppressing an increase in size of a package. The package includes a plurality of chips, a wiring layer, and a molding material. The plurality of chips includes an optical chip. The plurality of chips is mounted on the wiring layer. The molding material is disposed so as to surround the periphery of at least one chip of the plurality of chips, and the surface is flattened. The position of the flat surface of the molding material in the height direction may be substantially equal to the position of the top surface of at least one of the plurality of chips in the height direction. The optical chip may include at least one of a light receiving element and a light emitting element.