Stacked Optical Chip Package Structure for Warpage Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional package structures face challenges in maintaining flatness and coplanarity due to stresses between redistribution layers and the encapsulant layer during chip stacking, leading to warpage issues that limit their application.
Innovation Solution
A package structure comprising a first package with a redistribution layer, a chip, and a second redistribution layer, along with a second package that includes a substrate, adhesive layer, optical chips, and a third redistribution layer, where the optical chips are attached to the substrate through an adhesive layer and surrounded by an encapsulant layer, with the third redistribution layer electrically connected to the second redistribution layer, helping to balance stresses and improve flatness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If multiple chips are stacked in a conventional package structure to achieve miniaturization and high density, then the package area is reduced, but stresses between redistribution layers and encapsulant layer cause warpage and poor flatness control
Solution Approach 1:
The package structure is divided into multiple independent packages, each containing a subset of optical chips. By segmenting the overall package into smaller units with fewer chips each, the stress accumulation is reduced and flatness can be better controlled in each segment, while still achieving high density through the stacked configuration of multiple segments.
Solution Approach 2:
An adhesive layer is introduced as an intermediary between the substrate and optical chips, and between packages in the stacked configuration. This adhesive layer acts as a stress buffer that compensates for thermal expansion differences and reduces stress transmission, thereby preventing warpage and maintaining flatness in the stacked package structure.
2Ease of manufacture
If optical chips are attached directly to substrate without encapsulant layer, then manufacturing process is simplified, but optical surfaces are exposed and unprotected
Solution Approach 1:
The optical chips are nested within the encapsulant layer, which is formed as a surrounding structure that encloses and protects the optical surfaces. This nested configuration provides mechanical protection and environmental sealing while maintaining the compact integrated structure, balancing protection requirements with manufacturing feasibility.
3Reliability
If redistribution layers are made thicker to improve electrical connection, then electrical conductivity is enhanced, but stress between layers increases causing warpage
Solution Approach 1:
The thickness and material composition of redistribution layers are optimized to achieve the minimum required electrical conductivity while minimizing stress. By carefully controlling the parameters of the redistribution layer (thickness, conductivity, material properties), the patent achieves adequate electrical connection without excessive stress accumulation that would cause warpage.
Solution Approach 2:
The package structure employs composite materials in the redistribution layers and adhesive layers, combining materials with different mechanical and electrical properties. This allows the redistribution layer to provide sufficient electrical conductivity while the composite structure compensates for stress through material property matching and stress distribution.
Data Source
AI summary
A package structure and a manufacturing method thereof are provided. The package structure includes a first package including a first redistribution layer, at least one chip and a second redistribution layer, and at least one second package disposed on the first package and including a substrate, an adhesive layer, at least two optical chips, an encapsulant layer, and a third redistribution layer. The optical chips are attached to a surface of the substrate close to the first package through the adhesive layer, and each optical chip has an optical surface close to the substrate. The encapsulant layer is disposed on the surface and surrounds the optical chips. The third redistribution layer is disposed between the encapsulant layer and the second redistribution layer, in which the second redistribution layer is electrically connected to the optical chips through the third redistribution layer.