Wafer-Level Optical Deflector Double Etching Dicing Streets
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Solution Overview
Problem
Existing methods for manufacturing optical deflectors result in large device sizes due to the need for ceramic packages and the formation of through-silicon vias, which increase manufacturing costs and reduce yield, and may require redesigning the optical deflector chip to reduce size.
Innovation Solution
A wafer-level optical deflector assembly is formed with double etching processes to create narrow dicing streets, eliminating the need for a cap wafer and through-silicon vias, allowing for smaller device sizes and reduced manufacturing costs by using a silicon-on-insulator wafer with deep reactive ion etching and a transparent substrate to separate optical deflectors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a ceramic package is used to bond the optical deflector chip, then the chip is protected and assembled, but the package size increases due to required spacing for bonding wires
Solution Approach 1:
The patent merges the package substrate with the wafer carrier by forming both the optical deflector array and the package substrate on the same wafer using a single semiconductor manufacturing process. This integration eliminates the need for separate ceramic packaging and bonding wire spacing, allowing the package to be as small as the optical deflector chip itself.
Solution Approach 2:
The patent extracts and eliminates the traditional ceramic package component entirely by replacing it with an integrated package substrate formed on the wafer. This removes the need for separate packaging materials and the associated spacing requirements for bonding wires.
2Reliability
If through-silicon vias are formed to connect MEMS chips to external electrodes, then electrical connection is achieved, but manufacturing cost increases and yield decreases
Solution Approach 1:
The patent extracts and eliminates the through-silicon via process entirely by forming electrical connections through conventional planar semiconductor manufacturing techniques. The package substrate is formed with electrode pads that directly connect to the MEMS chip electrodes on the wafer surface, avoiding the need for vertical via formation through the silicon substrate.
Solution Approach 2:
The patent transitions from vertical electrical connections (through-silicon vias) to planar surface connections. By maintaining all electrical connections on the wafer surface during manufacturing and only performing wire bonding after dicing, the complex vertical via formation process is replaced with simpler two-dimensional routing.
3Area of stationary object
If the optical deflector chip size is reduced, then the entire device size decreases, but the chip requires redesign extending the development period
Solution Approach 1:
The patent creates a universal wafer-level platform where the package substrate and electrical connection structures are formed using standard semiconductor manufacturing processes that can accommodate different MEMS chip designs. This modular approach allows chip size optimization without requiring complete redesign of the packaging and interconnection system.
4Productivity
If dicing streets are made narrow to increase integration, then more devices fit on the wafer, but dicing becomes more difficult and may cause device damage
Solution Approach 1:
The patent performs preliminary dicing street formation through etching processes before the actual mechanical dicing operation. By pre-defining the dicing street locations and removing material in advance, the subsequent mechanical dicing requires less force and reduces the risk of damaging the devices, enabling narrower streets without increasing manufacturing difficulty.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the width of dicing streets, enhances integration, and lowers manufacturing costs by avoiding unnecessary packaging and defective assembly, while maintaining high manufacturing yield and optical deflector performance.
Implementation Method 1
the front surface side of the wafer is etched by using elements of the wafer-level optical deflector assembly as a first etching mask, to form a front-side dicing street
Implementation Method 2
using a silicon-on-insulator wafer with deep reactive ion etching
Data Source
AI summary
A wafer-level optical deflector assembly (406∼ 413) is formed on a front surface side of a wafer (401∼ 404). Then, the front surface side of the wafer is etched by using elements of the wafer-level optical deflector assembly, to form a front-side dicing street (Y1). Then, a transparent substrate (501) with an inside cavity (501a) is adhered to the front surface side of the wafer. Then, a second etching mask (405) is formed on a back surface side of the wafer. Then, the back surface side of the wafer is etched to create a back-side dicing street (Y2). Then, an adhesive sheet (505) with a ring-shaped rim (506) is adhered to the back surface side of the wafer. Then, the transparent substrate is removed. Finally, the ring-shaped rim is expanded to widen the front-side dicing street and the back-side dicing street to pick up optical deflectors one by one from the wafer.