Optical Delay Clock Jitter Cancellation for Low-Noise PLLs
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Solution Overview
Problem
High-frequency communication systems face challenges in reducing jitter and spurious tones in clock signals, leading to increased system cost and power consumption, particularly in high-speed wireline and wireless applications.
Innovation Solution
An electro-optical phase noise cancellation system using a photonic crystal-based optical delay line, combined with a Mach-Zehnder Interferometer and low-power resonant-CMOS driver, to generate ultra-low noise clocks by detecting phase differences and processing the clock signal through a voltage-controlled delay line.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a higher reference clock frequency is used to reduce phase noise in high-frequency PLLs, then phase noise is reduced, but system cost increases
Solution Approach 1:
The patent introduces an optical delay line as an intermediary component between the reference clock and the PLL. This optical delay line delays the reference clock signal by a controllable amount, allowing the PLL to achieve low phase noise at high output frequencies without requiring a proportionally high reference clock frequency. The optical domain acts as a mediator that enables precise delay control without the cost and complexity of ultra-high-frequency electrical components.
2Reliability
If an on-chip LC oscillator is implemented to reduce phase noise, then phase noise is reduced, but power consumption increases
Solution Approach 1:
The patent replaces the traditional electrical LC oscillator mechanism with an optical delay line-based phase noise cancellation system. The optical delay line uses photonic components rather than electrical resonators, fundamentally substituting the mechanical/electrical oscillation mechanism with an optical time-delay mechanism. This substitution achieves comparable or superior phase noise performance while consuming significantly less power, as optical components can store energy temporarily without continuous power input.
3Reliability
If optical delay is used for phase noise cancellation, then phase noise is reduced, but device complexity increases
Solution Approach 1:
The patent transitions from the electrical domain to the optical domain to solve the phase noise problem. By moving the delay function into the optical dimension, the system achieves precise, stable delays that are difficult to obtain in the electrical domain at high frequencies. This dimensional change allows for simpler overall system architecture despite the introduction of optical components, as the optical delay line provides functionality that would require complex electrical circuits to achieve.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The system effectively reduces phase noise and spurious tones in clock signals without significant power penalty, enabling efficient operation in high-speed communication systems while maintaining low power consumption.
Implementation Method 1
an optical modulator configured to modulate an optical signal based on the clock signal to obtain a modulated optical signal
Implementation Method 2
an optical delay configured to delay the modulated optical signal to obtain a delayed modulated optical signal
Implementation Method 3
a photo detector configured to convert the delayed modulated optical signal to an electrical signal
Data Source
AI summary
Techniques to reduce or eliminate phase noise and jitter from a noisy clock signal. A method includes generating an electrical clock signal, generating a delayed optical clock signal based on the electrical clock signal, detecting a phase difference between the electrical clock signal and the delayed optical clock signal, and processing, based on the phase difference, the electrical clock signal to obtain a reduced phase noise version of the electrical clock signal.