Semiconductor Optical Device Buried Layer Flatness

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Solution Overview

Problem

The existing semiconductor optical integrated devices face challenges in achieving optimal surface flatness and resin region quality due to gaps formed between buried semiconductor layers and end surfaces, which affect the performance and reliability of the device.

Innovation Solution

A method involving the use of specific mask patterns and etching processes to form stripe-shaped mesa structures and selectively grow buried semiconductor layers, ensuring that gaps are minimized and the surface flatness of the resin region is enhanced by burying both side surfaces of the mesa structures in different layers, such as semi-insulating semiconductor and resin, respectively.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If both side surfaces of the stripe-shaped mesa structure are buried in the same buried layer, then the manufacturing process is simplified, but gaps form between the buried layer and end surfaces resulting in poor surface flatness

Engineering Contradiction:
Improvemanufacturing process simplicityVSAvoidsurface flatness
Core Design Contradiction:
Ease of manufactureVSManufacturing precision

Solution Approach 1:

The patent divides the burial structure into two distinct segments: a first buried layer (semi-insulating semiconductor layer) for one side surface and a second buried layer (resin layer) for the other side surface. This segmentation allows each buried layer to be optimized independently, preventing gap formation and achieving high surface flatness while maintaining manufacturing feasibility through separate processing steps.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies different burial solutions to different regions of the device. The first buried layer is used where electrical isolation is needed, while the second buried layer is used where surface flatness and gap prevention are priorities. This localized approach allows each region to have the optimal burial structure for its specific requirements.

Inventive Principle:
Principle #3Local quality

2Device complexity

If gaps form between buried semiconductor layers and end surfaces, then the device structure is simpler, but the resin region quality deteriorates and device reliability decreases

Engineering Contradiction:
Improvedevice structure simplicityVSAvoiddevice reliability
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The patent performs preliminary actions by forming the first and second buried layers before forming the resin region. This ensures that the buried layers are already in place to prevent gap formation, thereby guaranteeing high resin region quality and device reliability from the outset of the manufacturing process.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent introduces a second buried layer (resin layer) as an intermediary between the semiconductor structure and the final resin region. This intermediary layer acts as a buffer that prevents direct contact and potential gap formation, ensuring smooth interfaces and high-quality resin regions.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Stability of the object's composition

If the same buried layer is used for both side surfaces, then material consistency is maintained, but the resin region forms with poor quality and defects

Engineering Contradiction:
Improvematerial consistencyVSAvoidresin region quality
Core Design Contradiction:
Stability of the object's compositionVSManufacturing precision

Solution Approach 1:

The patent applies different burial solutions to different regions of the device. The first buried layer is used where electrical isolation is needed, while the second buried layer is used where surface flatness and gap prevention are priorities. This localized approach allows each region to have the optimal burial structure for its specific requirements.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent employs a composite burial structure combining two different materials: a semi-insulating semiconductor layer and a resin layer. This composite approach leverages the advantages of both materials - the electrical isolation properties of the semiconductor layer and the surface-flatting capabilities of the resin layer - to achieve high-quality resin regions without defects.

Inventive Principle:
Principle #40Composite materials

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach improves the surface flatness and quality of the resin region, reducing defects and enhancing the performance and reliability of the semiconductor optical integrated device by preventing the formation of gaps between buried semiconductor layers and end surfaces.

Implementation Method 1

selectively growing a buried semiconductor layer on both side surfaces of the stripe-shaped mesa structure

Methodology Applied
Scientific EffectEpitaxial growth: Epitaxy

Data Source

PatentUS8637329B2Method for producing semiconductor optical integrated device
Publication Date: 2014.01.28 SUMITOMO ELECTRIC INDUSTRIES LTD
  • US8637329B2 patent drawing
  • US8637329B2 patent drawing
  • US8637329B2 patent drawing

AI summary

A method for producing a semiconductor optical integrated device includes the steps of forming a substrate product including first and second stacked semiconductor layer portions; forming a first mask on the first and second stacked semiconductor layer portions, the first mask including a stripe-shaped first pattern region and a second pattern region, the second pattern region including a first end edge; forming a stripe-shaped mesa structure; removing the second pattern region of the first mask; forming a second mask on the second stacked semiconductor layer portion; and selectively growing a buried semiconductor layer with the first and second masks. The second mask includes a second end edge separated from the first end edge of the first mask, the second end edge being located on the side of the second stacked semiconductor layer portion in the predetermined direction with respect to the first end edge of the first mask.