Optical Disc RLL Encoding With Selective Parity Modulation
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Solution Overview
Problem
Existing recording technologies face challenges in efficiently recording signals of run-length-limited codes on optical discs due to high latency and a significant increase in the number of parity bits, which affects encoding rate and DC characteristics.
Innovation Solution
A recording apparatus that implements run length modulation and DSV control to convert information signals into run-length-limited codes, adding a sync signal and generating parity signals using error correction schemes, while only modulating parity signals to minimize the increase in parity bits, thereby maintaining efficient encoding rates and DC characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If run length modulation and DSV control are applied to turbo codes or LDPC codes, then DC characteristics improve, but the number of parity bits increases significantly
Solution Approach 1:
The patent segments the information signal processing into two distinct parts: (1) information bits undergo run length modulation and DSV control to ensure DC characteristics, and (2) parity bits are generated separately from this modulated signal and then undergo separate run length modulation. This segmentation allows each component to be optimized independently, preventing the exponential increase in parity bits that would occur if the entire coded signal were subjected to run length limitation.
Solution Approach 2:
The patent extracts the run length modulation and DSV control operations from the parity bit generation process. Specifically, run length modulation is applied only to the information signal before parity generation, and then applied again to the generated parity bits themselves. This extraction prevents the compounding effect where run length constraints would be applied to already-constrained signals, which would dramatically increase the number of required parity bits.
2Reliability
If run length limitation is applied to parity bits, then transmission reliability improves, but encoding rate decreases
Solution Approach 1:
The patent applies run length modulation dynamically and selectively - first to the information signal to create a pre-modulated sequence, then generates parity bits from this sequence, and finally applies run length modulation only to the parity bits themselves. This dynamic, multi-stage approach ensures that run length constraints are satisfied for reliable transmission while minimizing the overhead introduced by additional parity bits, thereby maintaining higher encoding rates compared to applying run length constraints to the entire coded signal.
3Reliability
If extended bit insertion encoding is used to control DC component, then DSV control improves, but effective encoding rate decreases
Solution Approach 1:
The patent extracts DSV control from the parity bit generation process and applies it separately to the information signal before parity generation. By controlling the DSV of the pre-modulated information signal and then generating parity bits from this controlled signal, the system achieves effective DSV control without the need for extended bit insertion that would dramatically increase the number of parity bits and reduce the effective encoding rate.
Data Source
AI summary
A first run length encoder implements run length modulation of a first information signal to generate a second information signal of a run-length-limited code while subjecting the second information signal to DSV control and adding a sync signal to the second information signal to get a third information signal. A converter changes the third information signal into an NRZI signal including information code words. A parity generator produces original parity signals in response to the information code words in the NRZI signal, and combines the information code words and the original parity signals to form a first parity-added signal. A second run length encoder implements run length modulation of only the original parity signals in the first parity-added signal to convert the first parity-added signal into a second parity-added signal while subjecting the second parity-added signal to DSV control. The second parity-added signal is recorded on a recording medium.