Optical Drive Circuit Power Reduction via Segmented Emitter Followers

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Solution Overview

Problem

Existing drive circuits for optical communication systems face challenges in reducing power consumption while maintaining high-speed performance, leading to increased Joule heat generation and limited modulation speed due to slow response times in controlling current sources.

Innovation Solution

A drive circuit that amplifies differential input signals using a combination of emitter follower circuits, level shifters, and differential circuits with transistors and current sources to generate driving signals for optical modulators, optimizing voltage levels and current distribution to reduce power consumption and enhance modulation speed.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by stationary object

If the current source of the emitter follower circuit is controlled in accordance with an input signal to reduce power consumption, then power consumption is reduced, but the response speed decreases and modulation speed is limited

Engineering Contradiction:
Improvepower consumptionVSAvoidmodulation speed
Core Design Contradiction:
Use of energy by stationary objectVSSpeed

Solution Approach 1:

The drive circuit is divided into multiple emitter follower circuits (first, second, third, fourth) that operate in parallel, each handling different portions of the signal. This segmentation allows the circuit to achieve low power consumption in idle states while maintaining high-speed response when needed, as each segment can be independently controlled and optimized.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The circuit employs dynamic current control where the current sources of the emitter follower circuits are adjusted based on the input signal characteristics. During low-activity periods, current is reduced to minimize power consumption, while during high-speed modulation events, current is increased to maintain response speed, creating a dynamic balance between power efficiency and performance.

Inventive Principle:
Principle #15Dynamics

2Object-generated harmful factors

If power consumption of the drive circuit is reduced to suppress Joule heat generation, then heat generation is suppressed, but the ability to maintain high-speed performance deteriorates

Engineering Contradiction:
ImproveJoule heat generationVSAvoidhigh-speed performance
Core Design Contradiction:
Object-generated harmful factorsVSReliability

Solution Approach 1:

The drive circuit utilizes periodic switching of the emitter follower circuits, activating only the necessary circuits at specific times based on signal requirements. This periodic operation reduces average power consumption and associated heat generation while ensuring that high-speed performance is maintained during active periods when full performance is needed.

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

Different emitter follower circuits are assigned different current levels and operational characteristics based on their specific functions within the drive circuit. This local optimization allows certain circuits to operate at higher currents for speed-critical functions while others operate at lower currents for power efficiency, achieving both heat suppression and high-speed performance in different parts of the system.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS10642076B2Drive circuit
Publication Date: 2020.05.05 SUMITOMO ELECTRIC INDUSTRIES LTD
  • US10642076B2 patent drawing
  • US10642076B2 patent drawing
  • US10642076B2 patent drawing

AI summary

A level shift circuit lowers a voltage of a first differential signal by a second voltage value and outputs a lowered first differential signal as a second differential signal. A first differential circuit receives the first differential signal and outputs a third differential signal. A second emitter follower circuit receives the third differential signal at a base of a pair of second transistors. A second differential circuit receives the second differential signal at a base of a pair of third transistors. An output terminal is electrically connected to one of a first output node electrically connected to an emitter of the one of the second transistors and a collector of the one of the third transistors and a second output node electrically connected to an emitter of the another of the second transistors and a collector of the another of the third transistors and outputs a driving signal.