Coherent Optical DSP Messaging Channel for Pre-FEC Timing Sync
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Solution Overview
Problem
Current optical networking technologies lack a specification for an in-band messaging channel within the DSP frame structure, leading to non-deterministic timing delays and uncertainty in timing synchronization between nodes due to elastic FIFOs and FEC mappings, which are not addressed by existing protocol-based solutions like IEEE 1588-2008 and IEEE 1588-2008 over Ethernet.
Innovation Solution
A messaging channel is defined within the DSP frame at the Physical Media Attachment (PMA) sublayer, allowing for robust communication prior to Forward Error Correction (FEC), using reserved or padding symbols for exchanging messages like vendor identification and timing references, and employing techniques like parity checks and FEC to ensure reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If protocol-based timing synchronization (IEEE 1588-2008) is used, then timing information can be transferred between nodes, but non-deterministic timing delays and uncertainty occur due to elastic FIFOs and FEC mappings
Solution Approach 1:
The patent segments the timing synchronization function into two parts: (1) a messaging channel within the DSP frame structure for pre-FEC communication of timing references and identifiers, and (2) post-FEC protocol-based timing protocol (IEEE 1588-2008) for precise time transfer. This segmentation allows the pre-FEC messaging channel to establish deterministic timing references before data passes through elastic FIFOs and FEC mappings, while the post-FEC protocol handles precise time synchronization, thereby resolving the contradiction between timing accuracy and delay determinism.
Solution Approach 2:
The patent introduces a pre-FEC messaging channel as an intermediary layer within the DSP frame structure that operates before data enters elastic FIFOs and FEC processing. This intermediary channel carries timing references, vendor identifiers, and synchronization messages with deterministic timing characteristics, serving as a bridge between the physical layer and the protocol-based timing synchronization layer, thus eliminating non-deterministic delays while maintaining synchronization accuracy.
2Reliability
If a stable bi-directional physical link is established before communication, then reliable data transfer is achieved, but it takes milliseconds or seconds to set up the link (chicken-and-egg problem)
Solution Approach 1:
The patent implements preliminary action by establishing a pre-FEC messaging channel within the DSP frame structure that becomes available immediately upon frame transmission, before a stable bi-directional physical link is fully established. This channel allows nodes to exchange vendor identifiers, capability information, and timing references during the link setup phase, enabling faster interoperability verification and reducing the chicken-and-egg problem of waiting for complete link establishment before any communication can occur.
3Adaptability or versatility
If proprietary vendor implementations are used, then specific vendor requirements can be met, but interoperability and multi-vendor implementations are limited
Solution Approach 1:
The patent implements universality by creating a standardized pre-FEC messaging channel within the DSP frame structure that can carry vendor-specific information while maintaining multi-vendor interoperability. The messaging channel uses standardized frame structures and protocols that work across different vendors, while allowing flexible content to accommodate vendor-specific identifiers, capabilities, and requirements. This enables both universal compatibility and vendor-specific adaptability simultaneously.
Data Source
AI summary
Systems and methods are disclosed for providing a messaging channel within a coherent optical Digital Signal Processing (DSP) frame. A coherent optical modem generates a DSP frame comprising a plurality of symbols, including padding symbols and reserved symbols, and defines a messaging channel by modulating a message on at least a subset of the padding symbols or the reserved symbols. The messaging channel enables low-bandwidth information exchange prior to Forward Error Correction (FEC) decoding on the data path, facilitating communication before establishment of a stable bidirectional link. The message may be carried in padding symbols, reserved symbols randomized to avoid strong tones, or vendor-specific symbols assigned in the first DSP sub-frame. Example message content includes hardware details, identifiers, version information, counters, payload data, and I/Q tributary mapping. The approach is applicable to DSP frames compliant with ITU-T G.709.3 Amendment 1, OIF-400ZR, or OpenZR+ specifications.