Optical-Electrical Test Line Layout for Wafer-Level Chip Screening
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Solution Overview
Problem
The semiconductor industry faces challenges in accurately characterizing and identifying defective optical devices during the fabrication of integrated chips due to the inability to supply optical test signals, which reduces the effectiveness of wafer acceptance tests and decreases fabrication throughput.
Innovation Solution
Incorporating a test line structure with both optical and electrical input/output (I/O) structures on integrated chips, allowing for the provision of optical test signals to optical devices, enabling accurate characterization and early identification of defective wafers with a high number of optical device failures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If only electrical I/O structures are used for testing, then the test structure is simple, but optical devices cannot be properly characterized
Solution Approach 1:
The patent combines electrical I/O structures and optical I/O structures into a single integrated test line structure. The electrical I/O structures provide electrical test signals to electrical devices, while the optical I/O structures provide optical test signals to optical devices through waveguides. This merging allows comprehensive testing of both electrical and optical devices using a unified structure, resolving the contradiction between measurement precision for optical devices and structural simplicity.
Solution Approach 2:
The test line structure is designed with multi-functionality to serve both electrical and optical testing purposes. The electrical I/O structures can provide electrical test signals, while the optical I/O structures with integrated waveguides can provide optical test signals. This universal structure enables the same test line to characterize both electrical and optical devices, improving measurement precision without requiring separate complex testing systems.
2Productivity
If optical test signals cannot be supplied to optical devices, then the test structure remains simple, but defective wafers cannot be identified early
Solution Approach 1:
The patent implements preliminary testing by providing optical test signals to optical devices during the wafer fabrication process through the optical I/O structures and waveguides. This allows defective wafers to be identified early before packaging, enabling their discard at an early stage. The preliminary optical characterization prevents defective devices from proceeding to later packaging steps, thereby improving fabrication throughput by avoiding rework or yield loss.
3Ease of manufacture
If electrical I/O structures are placed directly on the semiconductor workpiece, then the electrical connection is direct, but optical I/O structures cannot be integrated
Solution Approach 1:
The patent introduces waveguides as intermediary structures to transmit optical signals from the optical I/O structures to the optical devices on the semiconductor workpiece. The waveguides act as mediators that bridge the gap between the optical I/O structures and the optical devices, enabling reliable optical signal transmission. This intermediary approach allows seamless integration of optical and electrical I/O structures on the same test line without compromising optical signal integrity.
Data Source
AI summary
Various embodiments of the present disclosure are directed towards an integrated chip including a test line structure disposed on a semiconductor workpiece. The test line structure includes a plurality of optical input/output (I/O) structures disposed within and/or on the semiconductor workpiece. The test line structure further includes a plurality of electrical I/O structures on the semiconductor workpiece. The plurality of optical I/O structures and the plurality of electric I/O structures are laterally spaced from one another along a line extending in a first direction.