Optical Frame-Aligned FEC Encoding for Simpler Clock Synchronization
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Solution Overview
Problem
Existing intra-board interconnection error correction schemes in optical transport networks, such as GFEC and staircase FEC, fail to meet the requirements for reliable high-rate transmission and complicate clock synchronization in optical port interfaces.
Innovation Solution
Implementing a data processing method that uses Reed-Solomon forward error correction encoding, where clock simplified padding data is padded into the target information bit, aligning the error correction encoding scheme with the frame structure to simplify clock design and improve error correction performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If GFEC or staircase FEC error correction schemes are used in existing intra-board interconnection designs, then error correction capability is provided, but clock synchronization complexity increases and transmission reliability at high rates deteriorates
Solution Approach 1:
The patent changes the data block length parameter from non-standard values to a standardized length that is an integer multiple of the frame structure. This parameter adjustment enables the error correction scheme to align with the existing frame structure, simplifying clock synchronization while maintaining high-rate transmission reliability
Solution Approach 2:
The patent creates a universal error correction scheme that works across different transmission rates by standardizing the data block length. This standardized approach can be applied universally to various intra-board interconnection scenarios without requiring rate-specific clock synchronization mechanisms
2Reliability
If staircase FEC is used for encoding and decoding in optical transmission, then error correction performance is improved, but clock processing complexity increases
Solution Approach 1:
The patent adjusts the data block length parameter to match the frame structure, enabling staircase FEC to operate without complex clock processing. By making the data block length an integer multiple of the frame length, the encoding and decoding operations align naturally with the frame boundaries, eliminating the need for complex clock synchronization
Solution Approach 2:
The patent segments the optical path data into standardized data blocks that align with the frame structure. This segmentation allows the error correction scheme to process data in discrete, frame-aligned units, simplifying the clock processing required for staircase FEC operations
3Productivity
If transmission rate of intra-board interconnection is increased, then transmission capacity is improved, but error correction performance of GFEC deteriorates
Solution Approach 1:
The patent changes the data block length parameter to a standardized value that works effectively at high transmission rates. This parameter optimization enables the error correction scheme to maintain high performance even as transmission rates increase, overcoming the limitations of GFEC at high speeds
Data Source
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AI summary
This application discloses a data processing method and a related apparatus. The method includes: obtaining a first data block, where the first data block is a data block obtained by dividing first optical path data; padding clock simplified padding data and the first data block into a target information bit in a first data frame to form target data, where the target information bit is an information bit that is preset in the first data frame and that is used to pad optical path data; encoding the target data by using a first error correction encoding scheme, to obtain a first code block that has a mapping relationship with the first data frame, where the first error correction encoding scheme matches a frame structure of the first data frame; and sending the first code block. According to the solutions of this application, error correction performance can be improved, and a clock design can be simplified.