Optical IC Packaging With Exposed Optical Zone for Wafer-Level Testing
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Solution Overview
Problem
Conventional Wafer Level Packaging technologies, such as wirebonding, face limitations in density and electrical performance at high frequencies for silicon photonics devices, and wafer-level testing of 3D structures is challenging, leading to increased costs.
Innovation Solution
A method for forming an optoelectronic device with an optical integrated circuit featuring an exposed optical zone, surrounded by an electrically insulating material and coupled with an electrical integrated circuit, using a step-like structure and electro-optical system with an electrical coupling network, allowing for wafer-level testing and improved connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wirebonding is used in conventional Wafer Level Packaging, then electrical connections can be established, but density and electrical performance at high frequencies are limited
Solution Approach 1:
The patent extracts the optical zone from beneath the electrically insulating material, creating an exposed optical zone that allows optical signals to pass through while electrical connections are established through redistribution layers. This separation enables independent optimization of optical and electrical pathways, overcoming the limitations of wirebonding for high-frequency applications.
Solution Approach 2:
The patent introduces redistribution layers as an intermediary structure between the optical integrated circuit and external electrical connections. These redistribution layers route electrical signals through the electrically insulating material without requiring wirebonds, thereby improving both density and high-frequency electrical performance.
2Reliability
If wafer-level testing is attempted on 3D structures, then early defect detection is possible, but testing becomes challenging and costs increase
Solution Approach 1:
The patent segments the testing process into distinct stages: wafer-level testing of the optical integrated circuit before packaging, and subsequent packaging of the tested device. This segmentation allows standard wafer-level testing techniques to be applied to the optical circuit while the electrical connections are established later through redistribution layers, reducing overall testing complexity.
3Reliability
If the optical zone is covered by electrically insulating material for electrical connections, then electrical integrity is maintained, but optical signal access is blocked
Solution Approach 1:
The patent extracts or removes the electrically insulating material specifically from the optical zone area, creating an exposed optical zone that allows optical signals to access the optical waveguides. The electrically insulating material remains in other areas to maintain electrical integrity, thus resolving the conflict between electrical protection and optical access.
Solution Approach 2:
The patent applies local quality by having the electrically insulating material cover only specific regions of the optical integrated circuit while leaving the optical zone exposed. This localized approach allows different areas of the device to have different properties: electrical insulation where needed and optical transparency where required.
Data Source
AI summary
An optoelectronic device includes an optical integrated circuit having a first surface and a second surface opposite the first surface. The optical integrated circuit has an optical zone of the first surface of the optical integrated circuit. The device includes an electrically insulating material disposed over the optical integrated circuit, where the electrically insulating material partially covers the first surface so as to expose the optical zone.