Optical Semiconductor IC Terminal Layout for Wafer-Level Testing
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Solution Overview
Problem
Existing cantilever probe cards for semiconductor integrated circuits cannot simultaneously accommodate optical and electrical testing due to structural limitations, preventing efficient wafer-level testing of optical semiconductor integrated circuits.
Innovation Solution
An optical semiconductor integrated circuit design that includes a combination of electrical input/output terminals around the chip periphery and optical input/output terminals in specific locations where electrical terminals are not present, allowing simultaneous optical and electrical testing using standard probe cards.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a general cantilever type probe card is used for electrical testing, then electrical terminals can be tested, but optical input/output terminals cannot be contacted due to structural limitations
Solution Approach 1:
The chip periphery is divided into distinct regions: electrical terminals are disposed on one periphery while optical terminals are disposed on another periphery where electrical terminals are not disposed. This spatial segmentation allows separate access paths for electrical and optical probes, enabling both testing types to be performed simultaneously without interference.
2Adaptability or versatility
If optical input/output terminals are added for optical testing, then optical testing capability is achieved, but the number of electrical terminals is limited to about 10 to 20
Solution Approach 1:
The solution transitions from a one-dimensional constraint (shared periphery space) to a two-dimensional layout by utilizing different peripheries of the chip. Electrical terminals are arranged on one periphery while optical terminals are arranged on another periphery, effectively adding a spatial dimension that accommodates both terminal types without limiting the quantity of electrical terminals.
3Quantity of substance
If electrical terminals are disposed around the chip periphery for high-density electrical testing, then the number of electrical terminals can be increased to over 100, but no region is available for optical probe contact
Solution Approach 1:
The chip periphery is segmented into dedicated electrical regions and optical regions. Electrical terminals are concentrated on specific peripheries to achieve high density (over 100 terminals), while other peripheries are designated for optical terminals, ensuring sufficient space for optical probe contact and maintaining both high electrical terminal capacity and optical testing capability.
Data Source
AI summary
An optical semiconductor integrated circuit of the present disclosure realizes efficient wafer level testing by including electrical input/output terminals disposed around a chip and optical input/output terminals in the periphery in which electrical input/output terminals are not disposed. The optical semiconductor integrated circuit chip includes a plurality of electrical input/output terminals in at least one peripheral portion of a chip region. The electrical input/output terminals may be disposed in a U shape around the three sides. The optical semiconductor integrated circuit chip further includes an optical input/output terminal on one side on which an electrical input/output terminal is not disposed. The optical input/output terminal may be a grating coupler formed on a substrate.