3D Chip Stack Cooling via Optical Interconnects and Coolant Flow
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Solution Overview
Problem
Conventional methods for cooling three-dimensional (3D) chip stacks are inefficient as they primarily rely on heat removal from the edges and heat sinks, which fail to rapidly dissipate heat from the center and increase spatial requirements, and are hindered by dense interconnections that inhibit coolant flow.
Innovation Solution
The implementation of a surface-to-surface optical interconnect system within a 3D chip stack, where optical paths between light emitting diodes facilitate data communication and sparse metal interconnects for power and ground, allowing for direct coolant flow between layers, thereby enabling effective thermal management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If heat sinks are added to one or more sides of the chips, then heat removal capability is improved, but spatial requirements increase and heat removal from the center of the chip stack remains insufficient
Solution Approach 1:
The patent transitions from conventional 2D edge-based cooling to 3D volumetric cooling by introducing coolant flow paths that pass through the interior of the chip stack. The coolant manifold system creates three-dimensional heat removal by delivering coolant to intermediate layers and extracting heat from the center region, rather than relying solely on surface-mounted heat sinks at the boundaries.
Solution Approach 2:
The cooling manifold system is nested within the chip stack structure itself. The coolant flow paths are integrated into the interlayer spaces and routed through the core of the stack, allowing the cooling infrastructure to be contained within the existing spatial envelope of the chip assembly rather than adding external bulk.
2Reliability
If dense interconnections are used to connect chips in the stack, then interconnect reliability is improved, but coolant flow is inhibited
Solution Approach 1:
The interconnection system is segmented into two distinct functional categories: electrical interconnects for data/power transmission and thermal interconnects for heat removal. The electrical interconnects (signal traces, vias, bumps) are separated from the thermal management function, which is handled by the dedicated coolant manifold system. This segmentation allows dense electrical interconnections without compromising coolant flow paths.
Solution Approach 2:
The patent introduces an intermediary cooling manifold system that mediates between the dense electrical interconnections and the coolant flow. The manifold acts as a separate thermal transport network that interfaces with chip surfaces and intermediate layers without interfering with the electrical interconnect structure, enabling both dense connectivity and effective cooling.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables rapid and efficient cooling of intermediate layers in 3D chip stacks by minimizing thermal interference from electrical connections and ensuring continuous coolant flow, enhancing thermal dissipation and reducing the risk of heat-induced failures.
Implementation Method 1
a first plurality of light emitting diodes formed at a surface of the first microchip; a second plurality of light emitting diodes formed at a surface of the second microchip
Implementation Method 2
optical paths connecting the first plurality of light emitting diodes to the second plurality of light emitting diodes to thereby provide surface-to-surface optical data communication
Implementation Method 3
coolant disposed in the aperture, the aperture configured to receive incoming coolant at an aperture inlet and to exit coolant at an aperture outlet
Implementation Method 4
enabling effective thermal management... ensuring continuous coolant flow, enhancing thermal dissipation
Data Source
AI summary
In one embodiment, the disclosure relates to a system of stacked and connected layers of circuits that includes at least one pair of adjacent layers having very few physical (electrical) connections. The system includes multiple logical connections. The logical interconnections may be made with light transmission. A majority of physical connections may provide power. The physical interconnections may be sparse, periodic and regular. The exemplary system may include physical space (or gap) between the a pair of adjacent layers having few physical connections. The space may be generally set by the sizes of the connections. A constant flow of coolant (gaseous or liquid) may be maintained between the adjacent pair of layers in the space.