Optical Interferometer Time-Space Multiplexing for Lower Hardware Overhead

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Solution Overview

Problem

Photonic processors face a significant hardware overhead due to the need for numerous hardware structures, which is limited by fabrication success fidelities and available size on the wafer, especially when processing a large number of optical modes.

Innovation Solution

An optical processor design that combines temporal and spatial multiplexing using optical delay lines and optical devices, reducing the number of required devices by rerouting optical signals through delay loops, particularly suitable for universal interferometers and other optical chips with repetitive hardware structures.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If numerous hardware structures are implemented to process a large number of optical modes, then the processing capability is improved, but the device complexity and fabrication difficulty increase significantly

Engineering Contradiction:
Improveprocessing capabilityVSAvoidhardware structures
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent introduces a temporal dimension by implementing delay lines that store optical signals in the time domain. This allows the same spatial hardware structures to be reused across multiple time steps, transforming a purely spatial architecture into a spatio-temporal one. The delay lines enable signals to be held and reprocessed, effectively adding a time dimension to the computational space.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent merges spatial multiplexing (multiple optical paths and components) with temporal multiplexing (delay lines and time-dependent routing) into a unified architecture. This combination allows the system to achieve higher processing capability by reusing the same hardware structures across different time steps, rather than requiring separate dedicated structures for each computational function.

Inventive Principle:
Principle #5Merging (Combining)

2Productivity

If the number of optical devices is increased to handle more optical modes, then the processing capacity is improved, but the available wafer size and fabrication success fidelity are exceeded

Engineering Contradiction:
Improveprocessing capacityVSAvoidwafer size
Core Design Contradiction:
ProductivityVSArea of stationary object

Solution Approach 1:

The patent implements periodic action through time-dependent routing and control switches that cycle through different configurations. The system uses periodic switching to direct optical signals through different paths at different time steps, allowing the same physical hardware to perform multiple computational functions sequentially. This temporal cycling enables high processing capacity without requiring proportionally large hardware arrays.

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

The patent changes the operational parameters of the optical system by introducing time-varying control of switches and modulators. By dynamically adjusting routing parameters and signal timing, the system achieves flexible reconfiguration of the optical network, allowing the same hardware to adapt to different computational requirements without physical reconfiguration or additional components.

Inventive Principle:
Principle #35Parameter changes

3Adaptability or versatility

If traditional spatial multiplexing is used to handle multiple optical signals, then the signal processing capability is improved, but the hardware overhead increases significantly

Engineering Contradiction:
Improvesignal processing capabilityVSAvoidhardware overhead
Core Design Contradiction:
Adaptability or versatilityVSQuantity of substance

Solution Approach 1:

The patent uses delay lines to create temporal copies of optical signals, allowing the same signal to be processed multiple times at different time steps. Instead of requiring separate hardware paths for each processing operation, the system creates time-delayed copies of the input signals and routes them through the same computational structures sequentially, dramatically reducing hardware overhead.

Inventive Principle:
Principle #26Copying

Solution Approach 2:

The patent implements universal, reconfigurable optical structures that can perform multiple computational functions depending on the switching configuration. The same array of beam splitters and modulators can be reconfigured through time-dependent control to implement different unitary transformations, making the hardware universally applicable to various computational tasks without requiring task-specific dedicated structures.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Achieves hardware-efficient processing with reduced hardware requirements, maintaining universality and scalability, suitable for both universal and non-universal interferometers, and other optical processors with repetitive structures.

Implementation Method 1

an optical network that connects the processor input ports to the processor output ports

Methodology Applied
Scientific EffectOptical propagation: Light

Implementation Method 2

Optical interferometers, e.g. universal or non-universal interferometers are commonly used in photonic chips or photonic processors

Methodology Applied
Scientific EffectOptical interference: Interference

Data Source

PatentEP4671860A1Optical processor with time-space-multiplexing design
Publication Date: 2025.12.31 Q ANT GMBH
  • EP4671860A1 patent drawingFigure 1~2
  • EP4671860A1 patent drawingFigure 3~5
  • EP4671860A1 patent drawing

AI summary

The invention relates to an optical processor (2), in particular to an optical interferometer, comprising: a plurality of processor input ports (5.1 to 5.4) for receiving input optical signals (4.1 to 4.4), a plurality of processor output ports (6.1 to 6.4) for emitting output optical signals (7.1 to 7.4), and an optical network (9) that connects the processor input ports (5.1 to 5.4) to the processor output ports (6.1 to 6.4) and comprises at least one layer (11) with a plurality of optical devices (10a-c) configured to process the input optical signals (4.1 to 4.4) from the processor input ports (5.1 to 5.4). The at least one layer (11) has a plurality of input ports (14.1 to 14.4) and a plurality of output ports (15.1 to 15.4) that are connected to the plurality of input ports (14.1 to 14.4) via optical delay lines (16.1 to 16.4). The invention also relates to an apparatus (1), comprising: an optical processor (2) as indicated above, a plurality of light sources (3.1 to 3.4) for generating the plurality of input optical signals (4.1 to 4.4) for the optical processor (2), and a plurality of optical detectors (8.1 to 8.4) for detecting the output optical signals (7.1 to 7.4) from the optical processor (2).