3D Optical Interposer I/O Chiplet for Shoreline-Free SerDes Layout
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Solution Overview
Problem
Current high bandwidth processors and switches face shoreline limitations due to signal integrity constraints, leading to increased complexity and manufacturing costs, as SerDes macros can only be placed near the edge, limiting bandwidth density and requiring complex board/system designs.
Innovation Solution
A 3D stacked die complex with an active optical interposer integrated with an I/O chiplet allows SerDes macros to be placed virtually anywhere, using photonic-electronic packages with PICs and EICs, enabling high-speed serialization and deserialization, and eliminating shoreline constraints.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If SerDes macros are placed near the edge to maintain signal integrity, then reliability is improved, but device complexity and manufacturing costs increase due to shoreline limitations
Solution Approach 1:
The patent transitions from a 2D planar arrangement where SerDes macros must be placed near the edge to a 3D stacked architecture using through-silicon vias (TSVs). This vertical dimension allows SerDes macros to be placed anywhere on the chip while maintaining signal integrity through controlled impedance paths in the TSVs, eliminating shoreline constraints and reducing board complexity.
Solution Approach 2:
The patent introduces an optical interposer as an intermediary component between the SerDes macros and external optical transceivers. This interposer with integrated optics serves as a mediator that handles signal routing and optical conversion, simplifying the overall system design and reducing the complexity of direct electrical connections across the board.
2Reliability
If SerDes macros are placed near the edge to maintain signal integrity, then reliability is improved, but bandwidth density decreases due to limited placement area
Solution Approach 1:
By moving from 2D edge placement to 3D vertical stacking with TSVs, the patent enables SerDes macros to utilize the entire chip area including the center region. This dimensional transition dramatically increases the number of SerDes macros that can be integrated, thereby increasing bandwidth density while maintaining signal integrity through the vertical interconnect structure.
3Adaptability or versatility
If complex board/system designs are used to overcome shoreline limitations, then adaptability is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent replaces complex mechanical/board-level signal routing with a photonic system using optical fibers and optical transceivers. This substitution eliminates the need for precise electrical signal routing across the board, as optical signals are immune to electromagnetic interference and can be routed more flexibly, reducing manufacturing precision requirements while maintaining adaptability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach increases bandwidth density per mm², reduces manufacturing complexity, and lowers costs by using area-optimized Extra Short Reach SerDes, supporting high-speed communication protocols like Ethernet and PCIe.
Implementation Method 1
Optical transceivers are devices that transmit and receive data using light signals, typically over optical fiber cables. Optical transceivers play a crucial role in telecommunications and data communication networks, converting electrical signals into optical signals for transmission and then converting them back into electrical signals at the receiving end.
Implementation Method 2
Wavelength division multiplexing (WDM) is a technology used in optical communication to transmit multiple signals simultaneously over a single optical fiber. WDM achieves this by using different wavelengths (colors) of light for each signal, allowing for efficient use of the fiber's bandwidth and significantly increasing the data-carrying capacity.
Data Source
AI summary
Described herein is a novel approach that leverages a 3D stacked die complex with an active optical interposer integrated with an I/O chiplet including high-speed serializer/deserializer (SerDes). By integrating silicon in this way, shoreline constraints are eliminated, allowing for the SerDes macros to be placed virtually anywhere on the I/O chiplet. The photonic-based interconnects described herein improve upon conventional approaches based on co-packaged optics (CPO), Linear-drive Pluggable Optics (LPO) and copper-based solutions in terms of bandwidth and power consumption. The interconnects described herein rely on photonic-electronic packages in which a PIC provides processing units (e.g., XPU), electronic switching chips or other types of application-specific integrated circuits (ASIC) with access to optical fiber-based networks while multiple SerDes provide high-speed serialization and deserialization.