Optical Link Data Interleaving for Long-Fade Error Correction
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Solution Overview
Problem
Current solutions for interleaving data blocks in high-speed optical communications between a satellite and an earth station are inadequate, particularly due to the high data rates and prolonged signal fading periods, which corrupt large numbers of adjacent data blocks, and existing standards like CCSDS's HPE are not well-suited for high-speed communications.
Innovation Solution
A device and method utilizing a control module and external memory with a cache memory to interleave and deinterleave data blocks, where the cache memory has multiple buffer areas of equal size to a frame, allowing for efficient grouping and sequential writing of interleaved blocks to external memory, optimizing performance by minimizing write access limitations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional interleaving solutions (3GPP, DVB-S2) are used, then error correction is improved, but the solution is not well-suited for high-speed optical communications at 10 Gbits/s with prolonged fading periods
Solution Approach 1:
The patent modifies the interleaving parameters specifically for optical communications by setting the interleaving depth to cover prolonged fading periods (hundreds of milliseconds) and adjusting block sizes to optimize performance at 10 Gbits/s data rates, making the solution adaptable to high-speed optical systems while maintaining error correction capability
2Reliability
If a large number of frames are interleaved to cover prolonged fading periods, then error correction is improved, but the device complexity increases
Solution Approach 1:
The patent segments the interleaving process into manageable blocks and frames, organizing data into structured units that can be processed systematically. This segmentation allows handling of large numbers of frames through organized memory structures and control logic, reducing device complexity while maintaining the ability to cover prolonged fading periods
Solution Approach 2:
The patent introduces an intermediary memory structure that temporarily stores interleaved blocks from multiple frames, acting as a buffer between the interleaving operation and error correction. This intermediary structure simplifies the overall device architecture by decoupling the interleaving complexity from the error correction logic
3Reliability
If small interleaving blocks are used to optimize interleaving power, then error correction is improved, but the data rate handling capability is reduced
Solution Approach 1:
The patent merges multiple small interleaving blocks into larger frames for transmission, while maintaining the fine-grained interleaving structure within each block. This merging approach allows the system to handle high data rates through efficient frame processing while preserving the error correction benefits of small, optimized interleaving blocks
Data Source
AI summary
A device (10) for interleaving data blocks for an optical communications system between a satellite and an earth station. The interleaving device (10) includes a control module (11), a cache memory (15) and an external memory (12). The cache memory (15) includes buffer areas (16). The control module (11) is configured to write each new frame of blocks (21) received in an available buffer area (16), to form (102) groups (22) of interleaved blocks from different blocks (21) belonging to different frames (20) stored in different buffer areas (16), and to write (103) each group (22) of interleaved blocks thus formed in a sequential area (13b) of the external memory (12).