Optical Link Data Interleaving for Long Fading Periods

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Solution Overview

Problem

Current data interleaving solutions for high-speed optical communications between a satellite and a ground station are inadequate due to the specific challenges of signal fading in the atmosphere, which causes significant data corruption, and existing standards like CCSDS's HPE are not well-suited for high-speed applications.

Innovation Solution

A device and method for interleaving data blocks using a "row/column" scheme with a control module and external memory, employing a cache memory to optimize write access and reduce the impact of signal fading, allowing for efficient error correction and improved data transmission at high speeds.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional interleaving solutions (3GPP, DVB-S2) are used, then the system is compatible with existing standards, but the interleaving is not sufficient for high-speed optical communications with fading periods of several hundred milliseconds

Engineering Contradiction:
Improveerror correction performanceVSAvoidsuitability for high-speed optical communications
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

The patent changes the interleaving parameters specifically for optical communications by interleaving a very large number of frames (several thousand) to match the fading periods of several hundred milliseconds in optical channels, while maintaining compatibility with existing error correction standards like LDPC codes

Inventive Principle:
Principle #35Parameter changes

2Reliability

If a large number of frames are interleaved to cover fading periods, then error correction performance improves, but the complexity of the interleaving mechanism increases

Engineering Contradiction:
Improveerror correction performanceVSAvoidinterleaving mechanism complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent segments the interleaving process into manageable units by defining a specific interleaving pattern that processes frames in an organized sequence, making the complex task of interleaving several thousand frames systematically manageable while maintaining effectiveness

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent performs preliminary interleaving of data blocks before transmission, organizing them in a specific row-column pattern that预先 distributes potential fading errors across different code blocks, so that when fading occurs, the errors are already dispersed and can be more effectively corrected

Inventive Principle:
Principle #10Preliminary action

3Use of energy by moving object

If small interleaving blocks are used to optimize interleaving power, then power consumption decreases, but the ability to cover large fading periods diminishes

Engineering Contradiction:
Improveinterleaving powerVSAvoidfading period coverage
Core Design Contradiction:
Use of energy by moving objectVSDuration of action of moving object

Solution Approach 1:

The patent merges multiple small interleaving blocks into a comprehensive interleaving scheme that covers several thousand frames, combining the power efficiency of small blocks with the fading coverage capability of large-scale interleaving through a systematic row-column approach

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentEP4197104B1Device and method for interleaving data blocks for an optical communication system between a satellite and an earth station
Publication Date: 2023.11.22 AIRBUS DEFENCE & SPACE SAS
  • EP4197104B1 patent drawingFigure 1~2
  • EP4197104B1 patent drawingFigure 3
  • EP4197104B1 patent drawingFigure 4

AI summary

The invention relates to a device (10) for interleaving data blocks for an optical communications system between a satellite and an earth station. The interleaving device (10) comprises a control module (11), a cache memory (15) and an external memory (12). The cache memory (15) comprises a plurality of buffer areas (16). The control module (11) is configured to write each new frame of blocks (21) received in an available buffer area (16), to form (102) groups (22) of interleaved blocks from different blocks (21) belonging to different frames (20) stored in different buffer areas (16), and to write (103) each group (22) of interleaved blocks thus formed in a sequential area (13b) of the external memory (12).