Optical Module MCU Bus Architecture for Driving Chip Control
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Solution Overview
Problem
In optical communication modules, managing multiple driving chips with the same chip address is complex, often requiring additional address decoders, which complicates the structure and may affect communication accuracy.
Innovation Solution
The optical module incorporates a microcontroller unit (MCU) with multiple serial clock (SCL) bus interfaces and a single serial data (SDA) bus interface, allowing the MCU to transmit clock and data signals to all driving chips with the same address, enabling them to respond and establish communication without auxiliary devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If an address decoder is added to manage multiple driving chips with the same chip address, then the ability to control multiple driving chips is improved, but the device complexity increases
Solution Approach 1:
The patent divides the clock signal transmission path into multiple independent SCL bus interfaces (first SCL bus interface, second SCL bus interface, etc.), each connected to different driving chips. This segmentation allows the MCU to independently address and control each driving chip through its dedicated clock interface, eliminating the need for an address decoder while maintaining the ability to manage multiple chips with the same address.
2Measurement precision
If an address decoder is added to identify driving chips with the same address, then the communication accuracy is improved, but the device complexity increases
Solution Approach 1:
The patent introduces multiple SCL bus interfaces as intermediary channels between the MCU and different driving chips. Each SCL bus interface serves as a unique communication channel that mediates the interaction between the MCU and a specific driving chip, enabling accurate identification and communication without requiring an address decoder.
3Device complexity
If multiple SCL bus interfaces are used to connect MCU with multiple driving chips, then the structure is simplified, but the communication reliability may be affected
Solution Approach 1:
The patent segments the communication channels by providing dedicated SCL bus interfaces for different driving chips. This segmentation ensures that clock signals and data transmission to each driving chip occur through independent, dedicated paths, preventing signal interference and maintaining communication reliability while keeping the overall structure simple.
Data Source
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AI summary
An optical module and a method of transmitting data in the optical module are provided in the present disclosure. According to an example, the optical module may comprise a micro controller unit (MCU) and N number of first driving chips having a same chip address. The MCU may be configured to have a serial data (SDA) bus interface and N number of first serial clock (SCL) bus interfaces. Each of the N number of the first driving chips may be configured to have a SDA bus interface which is configured to be connected with the SDA bus interface on the MCU and a SCL bus interface which is configured to be connected with one of the N number of the first SCL bus interfaces on the MCU.