Optical Module Packaging Structure With Short Chip Interconnects
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Solution Overview
Problem
Conventional lead bonding packaging processes struggle to achieve a short length of interconnection between photonic and electronic chips in optical communication modules, leading to increased packaging costs and complexity due to the complexity of through-silicon via (TSV) processes and chip stress issues.
Innovation Solution
A packaging structure that includes a redistribution layer and a plastic packaging structure with through vias, allowing for shorter conductive lines between chips, simplifying the production process, reducing costs, and avoiding the need for TSVs within the chips, while maintaining effective chip connectivity through micro bumps and vias.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If conventional lead bonding packaging process is used, then chip packaging can be achieved, but the length of interconnection between chips cannot be minimized
Solution Approach 1:
The patent transitions from planar lead bonding to three-dimensional vertical interconnection through TSV structures. The TSV enables vertical signal transmission through the substrate thickness direction, reducing the horizontal interconnection length between photonic and electronic chips while maintaining electrical connectivity.
Solution Approach 2:
The substrate is segmented into functional regions including TSV regions for vertical interconnection and stress relief regions with through holes. This segmentation allows different areas to serve specific purposes: TSV regions for signal transmission and through hole regions for stress management, thereby reducing overall interconnection length while simplifying the packaging process.
2Length of moving object
If TSV is disposed on photonic chip and electronic chip to reduce interconnection length, then chip stress problem occurs and effective utilization area is reduced
Solution Approach 1:
The substrate is divided into TSV regions and through hole regions. TSVs are concentrated in specific areas for vertical interconnection, while through holes are distributed in stress relief regions. This segmentation minimizes the area occupied by interconnection structures and prevents excessive stress concentration, preserving more effective chip utilization area.
Solution Approach 2:
Through holes filled with stress relief material serve as intermediaries between TSV regions and chip areas. These through holes act as stress relief structures that prevent stress concentration around TSVs, allowing TSVs to be implemented without significantly reducing the effective utilization area of the chip.
3Length of moving object
If TSV is disposed on chip to achieve short interconnection, then chip packaging costs increase due to complex process and stress safety region requirements
Solution Approach 1:
The substrate is segmented into TSV regions and through hole regions, allowing standardized processing steps to be applied to different areas. This segmentation simplifies the overall packaging process by enabling modular manufacturing approaches while achieving short interconnection lengths through vertical TSV structures.
Solution Approach 2:
The through holes in stress relief regions automatically serve dual purposes: they provide stress relief to prevent chip cracking and they simplify the TSV formation process by pre-defining areas where stress management is needed. This self-service approach reduces packaging process complexity while maintaining short interconnection lengths.
Data Source
AI summary
A packaging structure includes: a first redistribution structure, where a distribution layer is disposed in the first redistribution structure; a plastic packaging structure, where the plastic packaging structure wraps a surface of the first redistribution structure other than an upper surface, and each of the at least one through via penetrates an upper surface and a lower surface of the plastic packaging structure; and a first chip and a second chip, where the first chip and the second chip are disposed above the first redistribution structure and the plastic packaging structure, the first chip is connected to the second chip by using the distribution layer, and at least a part of lead-out ends of the first chip and at least a part of lead-out ends of the second chip are led from the upper surface of the plastic packaging structure to the lower surface.