Optically Coupled MOSFET Relay Layout for Low-Dead-Time Switching

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Solution Overview

Problem

Current semiconductor devices with multiple relay units face challenges in efficiently switching between alternating-current and direct-current signals due to variations in MOSFET characteristics and optical sensitivity, leading to increased dead time and reduced operation speed.

Innovation Solution

The semiconductor device incorporates a configuration with two relay units, where light emitting elements and light receiving elements are arranged in an antiparallel manner, with adhesion layers to ensure consistent light transmission and reduce variations in optical sensitivity, and MOSFETs are arranged on a common substrate to minimize variations in characteristic values.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If light emitting elements and light receiving elements are arranged in separate relay units, then signal transmission can be achieved, but variations in MOSFET characteristics and optical sensitivity increase dead time

Engineering Contradiction:
Improvesignal transmission reliabilityVSAvoiddead time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent merges the light emitting elements and light receiving elements into a single integrated relay unit structure, where the light emitting element is positioned directly above the light receiving element with minimal separation. This integration reduces the dead time by eliminating the time required for signal transmission between separate relay units, while maintaining reliable signal transmission through the direct optical coupling path.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent implements preliminary action by pre-positioning the light emitting element and light receiving element in precise alignment within the same relay unit before signal transmission begins. The adhesion layers are pre-applied to ensure consistent optical coupling, and the MOSFETs are pre-configured with optimized characteristics to minimize switching dead time, allowing the system to operate with reduced dead time from the start.

Inventive Principle:
Principle #10Preliminary action

2Measurement precision

If adhesion layers are applied between light emitting element and light receiving element, then optical sensitivity consistency is improved, but manufacturing complexity increases

Engineering Contradiction:
Improveoptical sensitivity consistencyVSAvoidmanufacturing complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent applies adhesion layers with uniform material composition and consistent thickness between the light emitting element and light receiving element. This homogeneous application ensures that optical sensitivity is consistent across different relay units, as the adhesion layer provides a standardized optical coupling interface that eliminates variations in light transmission characteristics.

Inventive Principle:
Principle #33Homogeneity

Solution Approach 2:

The patent optimizes the parameters of the adhesion layer, including its thickness, material composition, and optical properties, to achieve the desired optical sensitivity consistency. By carefully controlling these parameters within specific ranges, the patent maintains consistent light transmission while managing manufacturing complexity through standardized parameter specifications.

Inventive Principle:
Principle #35Parameter changes

3Stability of the object's composition

If MOSFETs are arranged on a common substrate, then variations in characteristic values are reduced, but thermal dissipation becomes more challenging

Engineering Contradiction:
ImproveMOSFET characteristic consistencyVSAvoidthermal dissipation
Core Design Contradiction:
Stability of the object's compositionVSTemperature

Solution Approach 1:

The patent segments the common substrate into distinct thermal management zones, with each MOSFET positioned over its own thermal via structure or heat sink region. This segmentation allows each MOSFET to dissipate heat independently through dedicated thermal pathways, preventing thermal interference between adjacent devices while maintaining the electrical and characteristic consistency provided by the common substrate.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces thermal via structures and heat dissipation layers as intermediary elements between the MOSFETs and the substrate. These intermediaries facilitate efficient heat transfer from the MOSFET junctions to the substrate and ultimately to the external environment, enabling the MOSFETs to maintain consistent characteristics by operating at stable temperatures despite being arranged on a common substrate.

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration reduces dead time by ensuring consistent charging current and improving thermal dissipation, enhancing the reliability and speed of signal switching between relay units.

Implementation Method 1

a light emitting element arranged above the first surface of the substrate

Methodology Applied
Scientific EffectLight emission: Light Emitting Diode

Implementation Method 2

a light receiving element arranged between the first surface of the substrate and the light emitting element

Methodology Applied
Scientific EffectPhotoelectric conversion: Photoelectric Effect

Data Source

PatentUS12199602B2Semiconductor device
Publication Date: 2025.01.14 KK TOSHIBA
  • US12199602B2 patent drawing
  • US12199602B2 patent drawing
  • US12199602B2 patent drawing

AI summary

According to one embodiment, a semiconductor device includes a substrate; a first transistor, a second transistor, a third transistor, and a fourth transistor; a first light emitting element and a second light emitting element; a first light receiving element configured to switch the first transistor and the second transistor to an ON state or to an OFF state; and a second light receiving element configured to switch the third transistor and the fourth transistor to the ON state or to the OFF state, wherein the first light emitting element and the second light emitting element are configured such that, when either one of the first light emitting element or the second light emitting element is turned to a lit state, the other one is turned to an unlit state.