Optical Multichip Package with Disaggregated SOC and Photonic I/O
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Solution Overview
Problem
Legacy semiconductor packaging architectures face challenges in scalability and performance due to the use of single large centralized SOC dies and complex electrical interfaces, which result in increased package form factor, power consumption, and design complexity.
Innovation Solution
The solution involves disaggregating the SOC into multiple SOC dies and co-packaging them with photonic integrated circuits (PICs) on a multichip package (MCP) using a stacked die structure, which simplifies electrical links and enables modular bandwidth and form factor scaling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a single large centralized SOC die is used, then device functionality is integrated, but package form factor increases and design complexity increases
Solution Approach 1:
The patent divides the single large centralized SOC die into multiple smaller SOC dies, each handling specific functions (e.g., CPU, GPU, memory controller). These segmented dies are then co-packaged with photonic integrated circuits on a shared substrate, reducing the overall package form factor while maintaining full device functionality through modular integration.
2Adaptability or versatility
If a single large centralized SOC die is used, then device functionality is integrated, but design complexity increases
Solution Approach 1:
The patent segments the SOC into multiple specialized dies, allowing each die to be designed and optimized independently by different teams or using different process nodes. This modular approach reduces overall design complexity while maintaining integrated functionality through standardized interconnect interfaces on the shared substrate.
Solution Approach 2:
The patent implements a universal shared substrate that provides standardized electrical and optical interconnects that can accommodate different SOC die configurations. This multi-functional platform allows the same substrate design to support various combinations of SOC dies and photonic circuits, reducing design complexity across product variants.
3Speed
If complex electrical interfaces are used, then high data rates are achieved, but power consumption increases
Solution Approach 1:
The patent replaces complex electrical interfaces with photonic integrated circuits that use optical signals for data transmission. This substitution eliminates resistive losses and signal integrity issues associated with electrical interconnects, achieving high data rates with significantly reduced power consumption, especially for inter-die communication.
4Speed
If electrical I/O is used, then device performance is maintained, but power efficiency decreases
Solution Approach 1:
The patent substitutes electrical I/O with optical I/O using photonic integrated circuits. The optical interfaces maintain device performance through high-bandwidth data transmission while dramatically improving power efficiency by eliminating the resistive losses and signal retransmission requirements inherent in electrical interconnects, particularly for long-distance or high-speed communication.
Data Source
AI summary
Embodiments described herein may be related to apparatuses, processes, and techniques related to disaggregating co-packaged SOC and photonic integrated circuits on an multichip package. The photonic integrated circuits may also be silicon photonics engines. In embodiments, multiple SOCs and photonic integrated circuits may be electrically coupled, respectively, into modules, with multiple modules then incorporated into an MCP using a stacked die structure. Other embodiments may be described and/or claimed.