Optical Network Overhead Processing Logic Multiplexing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing optical communication network technologies face challenges in efficiently processing overhead bytes for large-scale chips, leading to increased chip area, power consumption, and manufacturing costs due to the need for multiple overhead processing logics and restricted system clock frequency.
Innovation Solution
A method and device for overhead processing in optical networks that employs overhead storage and polling processes, using a single set of overhead processing logic to store and process overhead bytes in different address spaces, reducing chip area and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple overhead processing logics are instantiated correspondingly for each overhead type, then overhead processing capability is improved, but chip area increases and manufacturing cost rises
Solution Approach 1:
The patent merges multiple overhead processing logics into a single shared processing unit. Instead of having separate processing logic for each overhead type (J1, B3, C2, G1, H4, K3), the invention implements one unified overhead processing logic that can handle all overhead types by sequentially processing them according to their arrival at the overhead time slot. This merging approach directly reduces chip area while maintaining comprehensive overhead processing capability.
Solution Approach 2:
The overhead processing logic is designed with universal functionality to handle multiple types of overhead bytes (J1, B3, C2, G1, H4, K3) through a single processing unit. The processing logic can adaptively process different overhead types based on the incoming data, making the same hardware resource serve multiple functions. This multi-functionality allows the system to maintain high overhead processing capability without requiring separate dedicated logic for each overhead type, thereby reducing chip area and manufacturing cost.
2Productivity
If system clock frequency is increased to improve processing speed, then overhead processing efficiency is improved, but power consumption increases and manufacturing cost rises
Solution Approach 1:
The patent implements periodic action by processing overhead bytes in a sequential manner at regular intervals defined by the overhead time slot arrival. Instead of requiring high-speed parallel processing, the system processes overhead bytes one by one in a cyclic fashion according to their arrival pattern. This periodic processing approach allows the use of lower clock frequencies while maintaining effective overhead processing, thereby reducing power consumption and manufacturing cost.
Solution Approach 2:
The overhead processing logic operates continuously as overhead bytes arrive at the overhead time slot, processing them in a continuous stream without requiring high-speed intermittent processing bursts. The unified processing logic maintains continuous operation at a steady, lower clock frequency, which reduces power consumption compared to high-frequency intermittent processing while ensuring all overhead bytes are processed without delay.
Data Source
AI summary
A method for overhead processing of optical network and device thereof are disclosed, the device includes: an overhead memory, an overhead processor, and an overhead processor control module. The overhead processor control module is used for controlling the operation of the overhead memory and the overhead processor. The method includes: a system chip inputs the time slots of all overhead bytes that will be processed and descrambled data, and corresponding virtual container numbers, the overhead processor encodes the byte and stores all overhead byte of the same channel in the address of the same overhead memory; at the same time it stores in turn the overhead byte of different channels in different address spaces based on the virtual container numbers, so that an overhead processing logic performs a polling process. The method and device only use a set of overhead processing logic for the overhead of large capacity chips, and save the area and power consumption greatly, thereby reduce the production cost.