Optical Semiconductor Package Layout for Fast Signals and Low Warpage

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Existing semiconductor packages face limitations in signal transmission speed and reliability, particularly with electrical signals, necessitating a transition to optical signal transmission methods.

Innovation Solution

A semiconductor package design incorporating a first semiconductor chip with optical conversion devices, vertical wires, dummy chips, and wiring layers to convert optical signals into electrical signals, while maintaining structural balance and reducing manufacturing defects like dishing and erosion.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If electrical signals are transmitted through copper wires, then the wiring structure is simple and easy to manufacture, but the signal transmission speed is limited

Engineering Contradiction:
Improvesignal transmission speedVSAvoidwiring structure complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The patent replaces electrical signal transmission through copper wires with optical signal transmission through optical fibers. This substitution transitions from electrical fields to optical fields, enabling significantly higher signal transmission speeds while reducing interference and signal loss, thus resolving the speed limitation of traditional copper wiring.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patent introduces optical conversion devices as intermediary components that convert electrical signals to optical signals for transmission and then convert them back to electrical signals. This intermediary approach enables the benefits of optical transmission while maintaining compatibility with existing electrical circuitry.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Speed

If optical conversion devices are integrated into the semiconductor chip, then signal transmission speed is improved, but the chip area increases and manufacturing complexity increases

Engineering Contradiction:
Improvesignal transmission speedVSAvoidchip area
Core Design Contradiction:
SpeedVSArea of stationary object

Solution Approach 1:

The patent moves the optical conversion devices from the chip surface to the substrate level, utilizing the vertical dimension and substrate area rather than consuming precious chip surface area. This dimensional reorganization allows optical functionality to be added without increasing the chip footprint.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent divides the semiconductor package into functional modules: the chip contains only the core processing elements, while optical conversion devices are segregated onto the substrate. This segmentation allows each component to be optimized independently and reduces the area required on the chip itself.

Inventive Principle:
Principle #1Segmentation

3Productivity

If multiple chips are stacked vertically, then the device density is improved, but the structural balance deteriorates causing warpage

Engineering Contradiction:
Improvedevice densityVSAvoidstructural balance
Core Design Contradiction:
ProductivityVSStability of the object's composition

Solution Approach 1:

The patent introduces dummy chips as counterweight elements that compensate for the weight and thermal mass imbalance caused by the stacked semiconductor chips. These dummy chips are positioned to balance the structure, preventing warpage and maintaining structural integrity during manufacturing and operation.

Inventive Principle:
Principle #8Anti-weight (Counterweight)

Solution Approach 2:

The patent modifies the physical parameters of the package structure by adding dummy chips with specific materials and dimensions that match the thermal and mechanical properties of the active chips. This parameter adjustment ensures uniform heat distribution and stress balance across the stacked structure.

Inventive Principle:
Principle #35Parameter changes

4Stability of the object's composition

If dummy chips are added to balance the structure, then warpage is reduced, but the device complexity and manufacturing steps increase

Engineering Contradiction:
Improvestructural balanceVSAvoidpackage structure complexity
Core Design Contradiction:
Stability of the object's compositionVSDevice complexity

Solution Approach 1:

The dummy chips serve multiple functions simultaneously: they act as counterweights to prevent warpage, provide thermal management by dissipating heat, and serve as structural support elements. This multi-functionality reduces the need for additional separate components and simplifies the overall package design.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Enhances signal transmission speed and reliability by utilizing optical signals, improves heat distribution, and maintains structural integrity, reducing warpage and manufacturing issues.

Implementation Method 1

an optical conversion device that is in the first area and configured to receive an optical signal and converts it into an electrical signal

Methodology Applied
Scientific EffectPhotoelectric effect: Photoelectric Effect

Data Source

PatentUS20260018523A1Semiconductor package
Publication Date: 2026.01.15 SAMSUNG ELECTRONICS CO LTD
  • US20260018523A1 patent drawing
  • US20260018523A1 patent drawing
  • US20260018523A1 patent drawing

AI summary

A semiconductor package may include a first semiconductor chip including a first area, a second area, an optical conversion device that is in the first area, and vertical wires that are in the second area, the optical conversion device being configured to receive an optical signal and convert it into an electrical signal, a first dummy chip on the first semiconductor chip and at least partially overlapping with the first area, a second semiconductor chip at least partially overlapping with the second area, a wiring layer between the first and second semiconductor chips and including first wiring patterns that connect the vertical wires and the second semiconductor chip, and second wiring patterns that at least partially overlap with the first dummy chip, and a second dummy chip on the first dummy chip and on the second semiconductor chip.