Optical Package Stacking Without TSVs for Lower Thermal Stress
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Solution Overview
Problem
The integration of photonic and electronic dies in packaging for high-speed, low-power applications, such as Big Data and AI, faces reliability and cost issues due to thermal stress from differing coefficients of thermal expansion and the complexity and cost of fabricating through semiconductor vias (TSVs).
Innovation Solution
The implementation of electronic dies with dual-sided interconnect structures that enable backside power delivery, allowing photonic dies to be stacked without TSVs, thereby reducing thermal stress and fabrication complexity and costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If through semiconductor vias (TSVs) are used to connect stacked chips/dies, then electrical and physical connection is achieved, but reliability issues and increased cost are introduced due to thermal stress from differing coefficients of thermal expansion
Solution Approach 1:
The patent removes TSVs from the photonic die structure entirely, extracting the problematic through-semiconductor via technology that causes thermal stress. Instead, separate interconnect structures are used on the front and back surfaces of the photonic die to achieve electrical connection without penetrating the die substrate, thereby eliminating the source of thermal expansion stress.
2Ease of manufacture
If TSVs are implemented for connecting stacked chips, then interconnection is enabled, but fabrication complexity and cost increase
Solution Approach 1:
The patent divides the interconnection function into separate front-side and back-side interconnect structures rather than using a single TSV structure. The front surface interconnect handles signal transmission while the back surface interconnect handles power and ground, segmenting the complex TSV fabrication process into simpler, separate steps that reduce overall fabrication complexity.
Solution Approach 2:
The patent transitions from vertical through-die connections (TSVs) to a combination of front-surface and back-surface interconnects, effectively using the third dimension (back surface) to achieve interconnection without requiring high-precision vertical via fabrication through the entire die thickness, thereby reducing fabrication complexity.
Data Source
AI summary
An exemplary package includes a photonic die, an electronic die, and a package component. The electronic die has an electronic device layer disposed between a frontside interconnect structure and a backside interconnect structure. The backside interconnect structure is configured to deliver power to the electronic device layer. The photonic die, the electronic die, and the package component are stacked top-to-bottom. The backside interconnect structure of the electronic die is connected to the package component, and the photonic die is connected to the electronic die. In some embodiments, the photonic die and the electronic die are each free of through semiconductor vias, such as through silicon vias. In some embodiments, a frontside interconnect structure of the photonic die is connected to the frontside interconnect structure of the electronic die. In some embodiments, a backside interconnect structure of the photonic die is connected to the frontside interconnect structure of the electronic die.