Integrated Optical Package Wafer-Level Molding With Protected Alignment
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Solution Overview
Problem
Legacy optical packaging methods face challenges in integrating high-performance optical modules with smaller form factors, high-bandwidth, bandwidth density, and increased I/O counts, while dealing with issues of signal integrity, electrical I/O count, and contamination during the packaging process, leading to higher costs and lower yields.
Innovation Solution
The integration of photonic integrated circuits (PIC), electronic ICs (EIC), and optical coupling connectors (OCC) within a mold compound using Fan Out Wafer Level Package (FOWLP) or Omni Directional Interconnect (ODI) techniques, with protective caps and alignment features to maintain optical integrity, and performing packaging at the wafer or panel level to minimize contamination and handling issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If optical components are packaged using legacy methods, then manufacturing flexibility is maintained, but package size reduction and integration density are limited
Solution Approach 1:
The patent segments the optical package manufacturing process into wafer-level packaging stages, where multiple optical components are packaged simultaneously on a wafer substrate before dicing into individual packages. This segmentation enables compact package size while maintaining manufacturing flexibility through modular wafer-level operations.
Solution Approach 2:
The patent transitions from traditional discrete component packaging to wafer-level array packaging, adding the dimension of parallel processing. Multiple optical components are packaged in a two-dimensional array on the wafer, dramatically reducing package size while enabling high-volume manufacturing through dimensional scaling.
2Object-affected harmful factors
If components are handled individually during packaging, then precision alignment is achievable, but contamination risk and manufacturing cost increase
Solution Approach 1:
The patent merges multiple individual component packaging operations into a single wafer-level packaging process. Alignment marks and fiducials on the wafer substrate enable simultaneous precise alignment of multiple optical components during one packaging operation, reducing contamination risk while maintaining alignment precision through collective processing.
Solution Approach 2:
The wafer substrate provides self-alignment features through integrated alignment marks and fiducials that guide the packaging process. The wafer itself serves as the reference frame for positioning optical components, eliminating the need for external alignment apparatus and reducing handling-induced contamination while maintaining precision.
3Productivity
If wafer-level packaging is implemented, then productivity and yield are improved, but process complexity increases
Solution Approach 1:
The patent performs preliminary alignment mark formation and fiducial placement on the wafer substrate before the actual optical component packaging. This preliminary action establishes a reference framework that simplifies subsequent packaging operations, enabling high productivity while managing process complexity through staged preparation.
Solution Approach 2:
The wafer substrate serves multiple functions: as a mechanical support structure, as an alignment reference platform, and as a carrier for parallel packaging operations. This multi-functionality consolidates several process steps into one unified wafer-level process, improving productivity while the standardized wafer platform reduces overall process complexity through reusability.
Data Source
Figure 1A~1B
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AI summary
Embodiments herein relate to systems, apparatuses, or processes for creating an integrated photonics package that includes a photonics IC, an electronic IC, and an optical coupling connector that are molded within a single package. In embodiments, caps may be used to protect optical components during manufacture.