Optical Semiconductor Buried Layer Stress Reduction
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Solution Overview
Problem
Conventional optical semiconductor devices for Mach-Zehnder modulators face stress concentration and cracking issues in the buried layer due to temperature changes during processing and mounting, particularly at openings reaching the lower cladding layer, which affects the reliability of the device.
Innovation Solution
The optical semiconductor device incorporates a mesa structure at the boundary between the buried layer and the exposed semiconductor layer, with one side of the mesa structure covered by the buried layer and the other side exposed, reducing the thickness of the buried layer and distributing stress, thereby minimizing crack formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an opening is created in the buried layer to reach the lower cladding layer for electrode connection, then electrical connection is achieved, but stress concentration and cracks occur in the buried layer during heating and soldering
Solution Approach 1:
The patent divides the buried layer into multiple segments: a first buried layer covering the lower cladding layer and a second buried layer covering the upper cladding layer, separated by the electrode structure. This segmentation allows each buried layer to have optimized thickness and stress distribution, preventing cracks while maintaining electrode connection functionality.
Solution Approach 2:
The patent transitions from a single-plane opening structure to a multi-layer vertical structure by introducing a intermediate layer between the first and second buried layers. This dimensional change distributes the stress across multiple layers rather than concentrating it in a single opening, thereby improving crack resistance.
2Reliability
If the buried layer thickness is increased to provide greater distance between electrode and semiconductor, then electrical isolation is improved, but stress increases and crack formation becomes more prominent
Solution Approach 1:
The patent segments the thick buried layer into two separate buried layers (first and second buried layers) with an intermediate layer between them. This segmentation maintains the total thickness for electrical isolation while distributing the mechanical stress across multiple thinner layers, preventing crack formation.
Solution Approach 2:
The patent applies different thicknesses and material properties to different regions of the buried layer structure. The first buried layer has optimized thickness for isolation at the lower cladding region, while the second buried layer is optimized for the upper cladding region, allowing each region to have the precise quality needed without overall stress concentration.
3Ease of manufacture
If the opening in the buried layer is made to reach the lower cladding layer, then electrode connection is enabled, but the lateral side of the buried layer is exposed over several micrometers causing stress concentration at bent portions
Solution Approach 1:
The patent segments the single deep opening into two separate opening regions: a first opening for the lower cladding layer electrode connection and a second opening for the upper cladding layer electrode connection. This segmentation reduces the lateral exposure length of each buried layer, minimizing stress concentration at bent portions while maintaining electrode accessibility.
Solution Approach 2:
The patent resolves the lateral exposure problem by transitioning to a multi-layer vertical architecture. Instead of one long lateral exposure, the electrode connections are distributed across different vertical layers (first and second buried layers), reducing the lateral stress exposure length at any single location while maintaining manufacturing accessibility.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces stress in the buried layer, suppressing crack occurrence and enhancing the reliability of the optical semiconductor device by distributing thermal stress and preventing peeling and disconnection of electrodes.
Implementation Method 1
during heating in the wafer processing or soldering for mounting the device, the temperature changes of the optical semiconductor device cause stress in the buried layer resin
Data Source
AI summary
An optical semiconductor device includes a semiconductor substrate, a first semiconductor layer provided on the semiconductor substrate, and a mesa waveguide provided on the principal surface of the first semiconductor layer. The semiconductor device also includes a buried layer covering the upper surface of the first semiconductor layer. Part of the upper surface of the first semiconductor layer is exposed. A mesa structure provided at the boundary between a part of the first semiconductor layer is covered with the buried layer and a part of the first semiconductor layer is exposed. One side of the mesa structure is covered with the buried layer, and the other side is exposed. The optical semiconductor device can reduce the generation of stress in the buried layer, for example, to suppress the occurrence of cracks in the buried layer and enhance the reliability.