Optical Semiconductor Capacitor Integration via Back-Surface MIM Structure

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Solution Overview

Problem

Existing optical semiconductor devices face challenges in integrating a capacitor with sufficient capacitance due to space constraints from the optical element and electrode pad, limiting the effectiveness of noise component elimination.

Innovation Solution

The optical semiconductor device incorporates a capacitor on a resin layer covering the optical waveguides and signal electrodes, allowing for increased capacitor area and capacitance without expanding the device's footprint, using a metal-insulator-metal (MIM) structure with multiple metal layers and insulating films to enhance capacitance while maintaining device area.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of stationary object

If the capacitor is arranged in the remaining region of the semiconductor device other than the regions of the optical element and the electrode pad, then the device area is reduced, but the capacitance of the capacitor is restricted

Engineering Contradiction:
Improvedevice areaVSAvoidcapacitance
Core Design Contradiction:
Area of stationary objectVSQuantity of substance

Solution Approach 1:

The patent applies dimensionality change by forming the capacitor on the back surface of the substrate, utilizing the third dimension (depth/thickness) rather than competing for planar space. This allows the capacitor to be positioned below the optical element and electrode pad, effectively increasing the available area for the capacitor without increasing the overall device footprint, thereby resolving the contradiction between minimizing device area and maximizing capacitance.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Reliability

If a capacitor having a large capacitance is desired to eliminate high frequency noise components, then the noise elimination effectiveness is improved, but the area of the optical semiconductor device increases

Engineering Contradiction:
Improvenoise elimination effectivenessVSAvoiddevice area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent resolves this contradiction by positioning the capacitor on the back surface of the substrate, utilizing the vertical dimension to accommodate a large-capacitance component without increasing the planar device area. This dimensional repositioning allows the capacitor to achieve sufficient capacitance for effective high-frequency noise elimination while maintaining a compact device footprint.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent applies nesting by placing the capacitor structure within the vertical space of the device, specifically on the back surface beneath other components. This nested arrangement allows the capacitor to be integrated into the existing device structure, achieving large capacitance functionality without proportionally increasing the overall device area.

Inventive Principle:
Principle #7Nested doll (Nesting)

Data Source

PatentUS9563100B2Optical semiconductor device and method of producing the same
Publication Date: 2017.02.07 SUMITOMO ELECTRIC INDUSTRIES LTD
  • US9563100B2 patent drawing
  • US9563100B2 patent drawing
  • US9563100B2 patent drawing

AI summary

An optical semiconductor device including: a substrate having a principal surface; first and second optical waveguides disposed on the principal surface of the substrate, the first and second optical waveguides extending in a first direction, the second optical waveguide being arranged adjacent to the first optical waveguide in a second direction intersecting with the first direction; first and second signal electrodes disposed on the first and second optical waveguides; a resistor disposed on the principal surface, the resistor being arranged between the first optical waveguide and the second optical waveguide, the resistor being electrically connected to the first signal electrode and the second signal electrode; a resin layer disposed on the principal surface, top surfaces of the first and second signal electrodes, and the resistor; and a capacitor disposed on the resin layer, the capacitor being electrically connected to the resistor through an opening of the resin layer.