Optical Semiconductor Columnar Structure Parasitic Capacitance Reduction
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Solution Overview
Problem
Existing methods for manufacturing optical semiconductor elements, such as surface emitting semiconductor laser elements, face challenges in reducing parasitic capacitance without using expensive polymer materials, which increases manufacturing costs and complicates the fabrication process.
Innovation Solution
A method involving dry-etching of semiconductor layers on a semi-insulating substrate, followed by acid or alkali pretreatment to remove conductive layers, and forming interlayer insulating films and electrode pads directly on the substrate, using silicon nitride films with specific thickness and refractive indices to minimize parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If polymer materials are used to reduce parasitic capacitance, then parasitic capacitance is reduced, but manufacturing cost increases and fabrication process becomes complicated
Solution Approach 1:
The patent replaces expensive polymer materials with a cost-effective alternative: an inorganic insulating film (silicon oxide or silicon nitride) formed by standard semiconductor fabrication processes. This disposable-like approach uses conventional materials and processes rather than specialized polymer materials, achieving parasitic capacitance reduction without increasing manufacturing cost or complexity
Solution Approach 2:
The patent achieves parasitic capacitance reduction by controlling the thickness parameter of the inorganic insulating film (50-200 nm) and optimizing the electrode pad structure. By changing the film thickness and material properties rather than using polymer materials, the patent reduces parasitic capacitance while maintaining compatibility with existing manufacturing processes
2Manufacturing precision
If dry-etching is used to form columnar structure, then precise structure is achieved, but conductive layers remain on substrate causing increased parasitic capacitance
Solution Approach 1:
The patent extracts and removes the conductive layer from the substrate surface using acid or alkali treatment after dry-etching. This extraction step specifically targets and eliminates the unwanted conductive layer that would otherwise increase parasitic capacitance, while preserving the precisely formed columnar structure
Solution Approach 2:
The patent performs preliminary acid or alkali treatment to remove conductive layers before forming the inorganic insulating film. This preliminary action ensures that no conductive material remains on the substrate surface that could increase parasitic capacitance, preparing the surface optimally for subsequent insulation layer formation
3Productivity
If conventional manufacturing methods are used, then electrode pads are formed, but high parasitic capacitance limits high-speed modulation capabilities
Solution Approach 1:
The patent introduces an inorganic insulating film as an intermediary layer between the substrate and the electrode pad. This intermediary film with controlled thickness (50-200 nm) and specific material properties (silicon oxide or silicon nitride) reduces the parasitic capacitance at the electrode-substrate interface, enabling high-speed modulation while maintaining standard fabrication processes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Significantly reduces parasitic capacitance of electrode pads by up to 1/50, enhancing high-speed modulation capabilities without the need for costly polymer materials, thereby simplifying the manufacturing process and reducing costs.
Implementation Method 1
a region including an exposed surface of the first contact layer exposed by the dry-etching and an exposed surface of the substrate is pretreated with acid or alkali
Implementation Method 2
an interlayer insulating film is formed in a region including a side surface of the columnar structure, the exposed surface of the first contact layer, and the exposed surface of the substrate
Data Source
AI summary
A method of manufacturing an optical semiconductor element includes: a first step in which a columnar structure of a semiconductor layer formed on a semi-insulating substrate is formed; a second step in which the substrate is exposed in a periphery of the columnar structure; a third step in which a region including exposed surfaces of the first contact layer and the substrate is pretreated; a fourth step in which a first electrode is formed on the exposed surface of the first contact layer; a fifth step in which an interlayer insulating film is formed in a region including a side surface of the columnar structure and the exposed surfaces; a sixth step in which a first electrode wiring is formed on the interlayer insulating film; and a seventh step in which a second electrode wiring is formed on the interlayer insulating film.