Semiconductor Optical Sensor Interconnect via Vertical TSV Routing
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Solution Overview
Problem
The integration of semiconductor devices with optical sensors poses challenges in achieving optimal wafer-level interconnect due to space constraints, as redistribution layers (RDLs) cannot pass through the glass or light-receiving side of the die, making it difficult to achieve effective electrical interconnect for stacked packages.
Innovation Solution
A method involving the use of a laser to form openings in an insulating layer around the semiconductor die, allowing for the formation of interconnect structures that extend to the die, enabling electrical connections through the creation of through-hole vias (THVs) and redistribution layers (RDLs) on both the front and back sides, including the use of solder bumps and under-bump metallization (UBM) for signal routing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If RDLs are used for interconnect rerouting, then electrical interconnect is achieved, but RDLs cannot pass through the glass or light-receiving side of the die creating space constraints
Solution Approach 1:
The patent transitions from planar RDL routing to three-dimensional vertical interconnection through TSVs. Conductive vias are formed through the substrate thickness, enabling electrical connection between front-side and back-side circuitry, thereby resolving the space constraint issue while maintaining reliable electrical interconnect.
Solution Approach 2:
The interconnect structure is divided into multiple segments: front-side contact pads, through-substrate vias (TSVs), and back-side contact pads. This segmentation allows each component to be optimized independently, with TSVs handling vertical transport and RDLs handling lateral routing, thus overcoming the limitation of RDLs cannot pass through the substrate.
2Reliability
If TSVs are drilled through silicon area, then electrical interconnect for stacked packages is achieved, but TSVs may interfere with active circuitry
Solution Approach 1:
The substrate is designed with heterogeneous regions: active circuitry areas and passive TSV areas. The TSVs are strategically positioned in regions devoid of active devices, allowing vertical interconnection without interfering with functional circuitry. This local differentiation resolves the conflict between achieving stacked package interconnect and avoiding active circuitry interference.
3Adaptability or versatility
If optical sensors are placed in central active area, then optical sensing function is achieved, but additional space constraints are imposed on interconnect structure
Solution Approach 1:
The patent employs vertical TSV interconnection to route signals from optical sensors on the front side to back-side circuitry, bypassing the need for lateral RDL routing through the optical path. This three-dimensional routing approach accommodates central optical sensors while maintaining interconnect functionality.
Solution Approach 2:
TSVs serve as intermediary structures that transfer electrical signals vertically through the substrate, mediating between front-side optical sensors and back-side processing circuitry. This intermediary approach resolves the space constraint conflict by providing a dedicated vertical pathway that does not interfere with optical sensor operation or lateral RDL routing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach facilitates complete signal routing and interconnect between the front and back sides of semiconductor packages with optical sensors, enhancing integration and performance by reducing signal propagation and capacitance while allowing for miniaturization and robust packaging.
Implementation Method 1
forming an opening in the insulating layer using a laser
Data Source
AI summary
A semiconductor device includes a carrier and semiconductor die having an optically active region. The semiconductor die is mounted to the carrier to form a separation between the carrier and the semiconductor die. The semiconductor device further includes a passivation layer disposed over a surface of the semiconductor die and a glass layer disposed over a surface of the passivation layer. The passivation layer has a clear portion for passage of light to the optically active region of the semiconductor die. The semiconductor device further includes an encapsulant disposed over the carrier within the separation to form an expansion region around a periphery of the semiconductor die, a first via penetrating the expansion region, glass layer, and passivation layer, a second via penetrating the glass layer and passivation layer to expose a contact pad on the semiconductor die, and a conductive material filling the first and second vias.