Optical Signal Encapsulation for Clock Synchronization

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Solution Overview

Problem

Current methods for transmitting digital communications signals over optical links, such as CPRI over OTN, face challenges in synchronizing signals with different clock rates and latency requirements, leading to potential jitter and loss of data, especially in scenarios where fibre resources are scarce.

Innovation Solution

A method and apparatus that receive digital communications signals of different types, buffer them to synchronize clock rates, and frame them into a single optical channel using a common clock signal, avoiding jitter and optimizing fibre usage by allocating timeslots based on traffic weight and latency requirements.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If multiple digital communications signals with different clock rates are transmitted over a single optical channel, then fibre resource utilization is improved, but synchronization accuracy deteriorates due to clock rate differences and latency variations

Engineering Contradiction:
Improvefibre resource utilizationVSAvoidsynchronization accuracy
Core Design Contradiction:
ProductivityVSMeasurement precision

Solution Approach 1:

The optical channel is segmented into multiple timeslots, with dedicated timeslots allocated to different digital communications signals based on their traffic weight and latency requirements. This segmentation allows each signal to be transmitted with appropriate timing characteristics while sharing the common optical channel, thereby maintaining synchronization accuracy while improving fibre resource utilization.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The invention changes the timing parameters of signal transmission by allocating specific timeslots to different signals based on their clock rate characteristics and latency requirements. By adjusting the timeslot allocation parameters, the system accommodates signals with different clock rates while maintaining overall synchronization, resolving the contradiction between resource utilization and synchronization accuracy.

Inventive Principle:
Principle #35Parameter changes

2Measurement precision

If signals are buffered to synchronize clock rates, then synchronization accuracy is improved, but transmission latency increases

Engineering Contradiction:
Improvesynchronization accuracyVSAvoidtransmission latency
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The invention implements dynamic timeslot allocation where the timing and duration of buffer operations are adjusted based on the specific clock rate differences and latency requirements of each signal. Rather than using fixed buffering, the system dynamically adapts the buffering characteristics to minimize latency while achieving the necessary synchronization, thus resolving the contradiction between synchronization accuracy and transmission latency.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system performs preliminary timing adjustments and clock rate synchronization before signals are multiplexed onto the optical channel. By pre-synchronizing signals and allocating timeslots in advance based on their characteristics, the invention reduces the need for extensive buffering during transmission, thereby minimizing added latency while maintaining synchronization accuracy.

Inventive Principle:
Principle #10Preliminary action

3Device complexity

If a common clock signal is used for framing, then device complexity is reduced, but the ability to handle diverse signal types with different latency requirements deteriorates

Engineering Contradiction:
Improvesynchronization mechanism complexityVSAvoidhandling diverse signal types
Core Design Contradiction:
Device complexityVSAdaptability or versatility

Solution Approach 1:

The invention creates a universal framing mechanism using a common clock signal that can handle multiple types of digital communications signals with different latency requirements. By designing the timeslot allocation system to be signal-type-agnostic and based solely on traffic weight and latency parameters, the common clock mechanism achieves multi-functionality, allowing it to accommodate diverse signal types without increasing device complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The system maintains a common clock signal for framing but changes the timeslot allocation parameters dynamically based on the specific latency requirements and traffic characteristics of each signal type. This parameter-based adaptation allows the simple common clock mechanism to effectively handle diverse signal types, resolving the contradiction between device complexity and adaptability.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentEP3266131B1Encapsulating digital communications signals for transmission on an optical link
Publication Date: 2021.12.15 TELEFONAKTIEBOLAGET LM ERICSSON (PUBL)
  • EP3266131B1 patent drawingFigure 1
  • EP3266131B1 patent drawingFigure 2
  • EP3266131B1 patent drawingFigure 3

AI summary

A method (10) of encapsulating digital communications signals for transmission on a communications link, comprising steps: a. receiving a first signal of a first signal type and comprising a first clock signal and receiving a second signal of a second signal type, different to the first, and comprising a second clock signal different to the first clock signal, each clock signal having a respective clock value and accuracy (12); b. obtaining the first clock signal (14); c. obtaining a difference between at least one of the clock values of the clock signals and the accuracies of the clock signals (16) and buffering the second signal for a time at least long enough to compensate for the difference (18); and d. assembling the first signal and the buffered second signal into a frame comprising an overhead and a payload comprising a first portion and a second portion, mapping the first signal into the first portion and the second signal into the second portion (20), wherein step d. is performed using the first clock signal.