Optical Signal Package Structure With Fine RDL for Dense HPC Interconnects
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Solution Overview
Problem
High-performance computing (HPC) applications require high-density package structures with reduced line width and spacing of metal layers and dielectric thickness, which are costly to achieve with conventional through-silicon via (TSV) interposers.
Innovation Solution
A package structure incorporating a circuit board, package substrate, fine metal linewidth and spacing redistribution layer (RDL) substrate, electronic assembly, heat dissipation assembly, and optical fiber assembly, where the ASIC, EIC, and PIC assemblies are disposed on the fine metal RDL substrate and connected to the package substrate, utilizing smaller solder balls and underfill for cost-effectiveness and high-density integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a through-silicon via (TSV) interposer is added to achieve high-density package structure with reduced line width and spacing, then the metal layer line width and spacing are reduced, but the manufacturing cost increases significantly
Solution Approach 1:
The patent extracts and eliminates the expensive TSV interposer component from the package structure. Instead of using a TSV interposer substrate, the invention directly integrates redistribution layers (RDLs) onto the package substrate, removing the unnecessary intermediate layer while maintaining the required fine line width and spacing for high-density interconnects.
Solution Approach 2:
The package substrate is designed to perform multiple functions: it serves as both the mechanical support structure and the interconnection substrate with integrated RDLs. This multi-functional design eliminates the need for separate TSV interposer layers, reducing manufacturing complexity and cost while achieving the required signal routing capabilities.
2Productivity
If the thickness of dielectric layer of redistribution circuit layer is reduced to achieve high-density packaging, then the package density increases, but the manufacturing precision requirements increase
Solution Approach 1:
The patent changes the dielectric layer thickness parameter to be reduced, enabling higher package density. By optimizing this critical dimension parameter, the invention achieves compact high-density packaging while maintaining manufacturability through appropriate material selection and process control.
3Reliability
If VCSEL sources are electrically connected to pads by solder bumps, then the electrical connection is established, but the optical efficiency may be affected
Solution Approach 1:
The patent introduces an intermediary reflective layer between the solder bumps and the VCSEL sources. This intermediary layer serves as a optical reflector that redirects light away from the solder bumps, preventing optical energy loss while maintaining the electrical connection function of the solder bumps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution meets the requirements for high-density package structures while reducing costs compared to conventional TSV interposers, maintaining high optical efficiency and effective heat dissipation.
Implementation Method 1
a plurality of vertical cavity surface emitting laser (VCSEL) sources, wherein the VCSEL sources are arranged in an array on the base
Implementation Method 2
The VCSEL sources are electrically connected to the pads of the base by the solder bumps
Implementation Method 3
The heat dissipation assembly is disposed on the electronic assembly
Data Source
AI summary
A package structure includes a circuit board, a package substrate, a fine metal L/S RDL-substrate, an electronic assembly, a photonic assembly, a heat dissipation assembly, and an optical fiber assembly. The package substrate is disposed on and electrically connected to the circuit board. The fine metal L/S RDL-substrate is disposed on and electrically connected to the package substrate. The electronic assembly includes an application specific integrated circuit (ASIC) assembly, an electronic integrated circuit (EIC) assembly, and a photonic integrated circuit (PIC) assembly which are respectively disposed on the fine metal L/S RDL-substrate and electrically connected to the package substrate by the fine metal L/S RDL-substrate. The heat dissipation assembly is disposed on the electronic assembly. The optical fiber assembly is disposed on the package substrate and electrically connected to the package substrate and the PIC assembly. A packaging method of the VCSEL array chip is presented.


