Optical Switch Node Translator Using Hash Checksums

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Existing methods for updating control module components with a different command set from the system software are resource-intensive and inefficient, particularly in FPGA systems with limited resources, requiring extensive memory and comparator usage.

Innovation Solution

A method using a hash function in a low-cost field programmable gate array to identify and translate byte sequences without read/write memory cells, enabling software-transparent communication by transforming byte sequences into checksum values for configuring tributary interface modules within optical switch nodes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If stored byte sequences are compared directly in FPGA to identify operating modes, then identification accuracy is achieved, but resource consumption (memory and logic blocks) increases significantly

Engineering Contradiction:
Improvebyte sequence identification accuracyVSAvoidFPGA resource consumption
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent segments the byte sequence identification process into two stages: first computing a checksum value from the received byte sequence using a hash function, then comparing this condensed checksum against stored checksum values. This segmentation reduces the identification data from potentially long byte sequences to compact checksum values, dramatically reducing FPGA memory requirements while maintaining identification accuracy.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a checksum value as an intermediary element between the received byte sequence and the stored reference sequences. Instead of directly comparing long byte sequences, the system computes checksums as intermediate representations that preserve identification capability while occupying minimal FPGA resources. This intermediary approach resolves the contradiction between accurate identification and resource efficiency.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Adaptability or versatility

If hardware components are updated with new command sets, then hardware functionality is improved, but system software reprogramming is required

Engineering Contradiction:
Improvehardware command set compatibilityVSAvoidsystem reprogramming complexity
Core Design Contradiction:
Adaptability or versatilityVSEase of manufacture

Solution Approach 1:

The translator apparatus acts as an intermediary layer between the system software and hardware components with different command sets. It receives byte sequences from the software, computes their checksums, compares against stored checksums to identify the intended operating mode, then translates into the appropriate command for the hardware. This intermediary translation mechanism enables hardware updates without requiring software reprogramming.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent creates a virtual copy of the command set translation functionality through the translator apparatus, which maintains a stored set of byte sequences and their corresponding checksums. This copied reference data allows the system to recognize and translate various command formats without modifying the original system software, enabling flexible hardware updates.

Inventive Principle:
Principle #26Copying

3Reliability

If complete byte sequence comparison is performed, then identification reliability is ensured, but processing time increases

Engineering Contradiction:
Improvemode identification reliabilityVSAvoididentification processing time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent segments the identification process into checksum computation and checksum comparison phases. By first transforming the complete byte sequence into a condensed checksum value, the system reduces the amount of data that needs to be compared. This segmentation maintains identification reliability through the mathematical properties of checksum functions while dramatically reducing processing time by comparing compact values instead of long sequences.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS9288558B2System for translating instructions in a switch node
Publication Date: 2016.03.15 INFINERA CORP
  • US9288558B2 patent drawing
  • US9288558B2 patent drawing
  • US9288558B2 patent drawing

AI summary

A control module for an optical switch node, comprising a TIM having a plurality of operating modes in which a first mode is identified by a first byte sequence; a communication interface unit transmitting a second byte sequence for placing the TIM in the first mode, the first byte sequence different from the second byte sequence, and a gate array receiving the second byte sequence, storing a list of predetermined unique values, each value indicative of a particular operating mode command, receiving at least a portion of the second byte sequence and receiving instructions to apply an algorithm to at least a portion of the second byte sequence to transform the portion into a checksum value, comparing the checksum value to the list to determine the operating mode command, and transmitting the first byte sequence to the TIM to place the TIM into the first mode.