Optical Network Switching Frame Buffer for Simultaneous Time Slot Handling
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Solution Overview
Problem
The increasing bandwidth of transponder switches in optical networks leads to increased design and layout complexity of switching circuitry, which is not effectively addressed by existing technologies.
Innovation Solution
The implementation of a multi-port memory switch with write and read ports, utilizing one-read-one-write memories and multiplexers to simultaneously switch multiple data units across multiple time slots, allowing for increased bandwidth while maintaining efficient memory usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the bandwidth of the transponder switch is increased, then the switching capability is improved, but the design and layout complexity of the switching circuitry increases
Solution Approach 1:
The patent divides the switching circuitry into multiple independent memory modules, each handling a portion of the data stream. By segmenting the overall switching function across multiple smaller memory units, the system achieves higher total bandwidth while keeping individual module complexity manageable. Each memory module operates independently, allowing parallel processing of multiple time slots.
Solution Approach 2:
The patent introduces a time-slot dimension to the switching architecture, allowing multiple data units to be switched simultaneously across different time slots. This temporal multiplexing approach enables the system to increase bandwidth by utilizing time as an additional resource dimension, rather than simply expanding spatial circuitry complexity.
2Productivity
If multiple data units are switched simultaneously across multiple time slots, then the switching bandwidth is doubled, but the memory size requirements increase
Solution Approach 1:
The patent segments the memory into multiple smaller memory modules rather than using a single large memory. Each memory module handles a specific time slot or data unit, allowing the system to achieve high bandwidth through parallel access to multiple small memories. This segmentation reduces the complexity of individual memory units while maintaining the total capacity needed for high-speed switching.
Solution Approach 2:
The patent employs periodic switching across multiple time slots, where data units are read and written in alternating time periods. This periodic action allows the system to maintain high bandwidth by sequentially accessing different memory modules in a time-division manner, effectively utilizing memory resources without requiring all memories to be simultaneously accessible.
Data Source
AI summary
A switching frame buffer is described in which data units within a sequence of time slots, of a frame, may be simultaneously input and output at ports of the switching frame buffer. In one implementation, a write port may receive data units within a single cycle of the switch. A number of memories may be provided, where first selected ones of the memories constitute memory groups and second selected ones of the memories constitute a memory subsets, each of the memory groups including a corresponding one of the memory subsets. The write port may supply each of a number of copies of the data units to a corresponding one of the memory subsets. Multiplexers may be associated with the groups of the memories and a read port may receive one of the copies of a number of the data units from different ones of the multiplexers.