Optical Receiver Threshold Compensation for Asymmetrical Noise
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Solution Overview
Problem
Asymmetrical optical noise in optical fiber datalinks results in higher bit error rates for differential '1' bits due to uneven eye heights after optical-to-electrical conversion, necessitating adjustment of zero-crossing points to balance signal quality.
Innovation Solution
The implementation of two identical voltage-mode DAC circuits at the optical receiver front end, coupled to differential input nodes, generates adjustment signals to set zero-crossing points for positive and negative data, pulling up the zero-crossing point of positive data and pulling down that of negative data, while using high-value resistances and AC coupling capacitances to reduce power consumption and signal drift.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional optical-to-electrical conversion is used without threshold adjustment, then the circuit structure is simple, but the eye heights of differential bits are unbalanced resulting in higher bit error rate
Solution Approach 1:
The patent divides the threshold adjustment function into two separate DAC circuits, each handling one differential signal path independently. This segmentation allows precise control of each path's zero-crossing point while maintaining overall system balance, resolving the contradiction between reliability improvement and circuit complexity.
Solution Approach 2:
The patent introduces DAC circuits as intermediary components between the optical-to-electrical conversion stage and the signal processing stage. These intermediaries generate adjustment signals that balance the eye heights of differential bits without requiring complex restructuring of the entire circuit, thus improving reliability while controlling complexity.
2Use of energy by moving object
If high-value resistances and AC coupling capacitances are used in the DAC circuits, then power consumption is reduced to less than 1 mA, but signal drift may increase
Solution Approach 1:
The patent carefully selects and optimizes the parameter values of resistances and capacitances in the DAC circuits. By using high-value resistances combined with AC coupling capacitances, the design achieves low power consumption (less than 1 mA) while the AC coupling blocks DC drift, thus resolving the contradiction between energy efficiency and signal stability.
3Reliability
If zero-crossing points are adjusted to balance eye heights, then differential signal quality is improved, but additional adjustment circuitry is required
Solution Approach 1:
The DAC circuits serve multiple functions: they generate threshold adjustment signals, control zero-crossing points, and balance eye heights across differential paths. This multi-functionality allows the patent to improve signal quality while minimizing the addition of dedicated adjustment circuitry, as the DACs perform multiple roles within a single component type.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces power consumption to less than 1 mA while balancing eye heights and decreasing bit error rates, achieving improved signal quality by equalizing differential data signals.
Implementation Method 1
an optical-to-electrical conversion circuit configured to produce first and second differential electrical data signals
Data Source
Figure 1~2
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AI summary
An optical data circuit includes threshold adjustment circuits to perform threshold adjustment compensation of asymmetrical optical noise. The optical data circuit includes an optical-to-electrical conversion circuit configured to produce first and second differential electrical data signals, at respective first and second electrical nodes, in response to an optical data signal. First and second digital-to-analog converter (DAC) circuits are each respectively coupled to the first and second electrical nodes and configured to respectively generate first and second adjustment signals. The first and second DAC circuits are configured to adjust the first and second differential electrical data signals such that a zero-crossing point of positive data is pulled up in response to the first adjustment signal and a zero-crossing point of negative data is pulled down in response to the second adjustment signal.